Invention Grant
- Patent Title: Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication
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Application No.: US17001525Application Date: 2020-08-24
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Publication No.: US12108595B2Publication Date: 2024-10-01
- Inventor: Sumit Ashtekar , Rahul Ramaswamy , Walid Hafez , Hector M. Saavedra Garcia
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01H85/02 ; H01L29/66 ; H01L29/78 ; H10B20/20

Abstract:
A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.
Public/Granted literature
- US20220059552A1 INTEGRATED FUSE IN SELF-ALIGNED GATE ENDCAP FOR FINFET ARCHITECTURES AND METHODS OF FABRICATION Public/Granted day:2022-02-24
Information query
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