公开(公告)号：US11430873B2

公开(公告)日：2022-08-30

申请号：US16147707

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423

Abstract: A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

公开(公告)号：US11342232B2

公开(公告)日：2022-05-24

申请号：US16016415

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L21/8252 ,  H01L27/06 ,  H01L27/02 ,  H01L29/872 ,  H01L21/02 ,  H01L29/778

Abstract: A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.

公开(公告)号：US11329132B2

公开(公告)日：2022-05-10

申请号：US16016406

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8252 ,  H01L21/306 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

公开(公告)号：US09748327B2

公开(公告)日：2017-08-29

申请号：US15129794

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid Hafez ,  Chia-Hong Jan

IPC: G11C11/00 ,  H01L45/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/66

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/24 ,  H01L29/785

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

公开(公告)号：US11552075B2

公开(公告)日：2023-01-10

申请号：US16147706

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L27/07 ,  H01L29/20 ,  H01L29/51 ,  H01L29/49 ,  H01L27/02 ,  H01L29/66 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778

Abstract: A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.

公开(公告)号：US10763209B2

公开(公告)日：2020-09-01

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman Olac-Vaw ,  Walid Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/78 ,  H01L23/525 ,  H01L29/423 ,  H01L29/66 ,  G11C17/16 ,  H01L21/768 ,  H01L27/112

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US20200176582A1

公开(公告)日：2020-06-04

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US20200091285A1

公开(公告)日：2020-03-19

申请号：US16130911

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/20 ,  H01L29/51 ,  H01L21/8236

Abstract: Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC.

公开(公告)号：US20170207312A1

公开(公告)日：2017-07-20

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L23/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US11610971B2

公开(公告)日：2023-03-21

申请号：US16222976

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Johann Rode ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/205 ,  H01L29/10 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/423 ,  H01L29/207

Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.