Invention Grant
- Patent Title: Memories having vertically stacked conductive filled structures
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Application No.: US17071980Application Date: 2020-10-15
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Publication No.: US12114492B2Publication Date: 2024-10-08
- Inventor: Jordan D. Greenlee , John Mark Meldrim , Everett A. McTeer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- The original application number of the division: US16443491 2019.06.17
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H01L21/285 ; H10B41/27 ; H10B43/10 ; H10B41/10

Abstract:
Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
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