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公开(公告)号:US11894305B2
公开(公告)日:2024-02-06
申请号:US17658907
申请日:2022-04-12
发明人: Jordan D. Greenlee , John D. Hopkins , Rita J. Klein , Everett A. McTeer , Lifang Xu , Daniel Billingsley , Collin Howder
IPC分类号: H01L23/535 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
CPC分类号: H01L23/535 , H01L21/76805 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L23/53257 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
摘要: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号:US20230387229A1
公开(公告)日:2023-11-30
申请号:US17804530
申请日:2022-05-27
发明人: Everett A. McTeer , Farrell M. Good , John M. Meldrim , Jordan D. Greenlee , Justin D. Shepherdson , Naiming Liu , Yifen Liu
IPC分类号: H01L29/423 , H01L21/28 , H01L27/11582
CPC分类号: H01L29/4234 , H01L29/40117 , H01L27/11582
摘要: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号:US11742282B2
公开(公告)日:2023-08-29
申请号:US16988422
申请日:2020-08-07
发明人: Jordan D. Greenlee , Rita J. Klein , Everett A. McTeer , John D. Hopkins , Shuangqiang Luo , Song Kai Tan , Jing Wai Fong , Anurag Jindal , Chieh Hsien Quek
IPC分类号: H01L23/522 , H01L21/768 , H10B43/27 , H01L23/532
CPC分类号: H01L23/5226 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H10B43/27 , H01L23/53209 , H01L23/53266
摘要: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.
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公开(公告)号:US20210202710A1
公开(公告)日:2021-07-01
申请号:US17180312
申请日:2021-02-19
发明人: David Ross Economy , Rita J. Klein , Jordan D. Greenlee , John Mark Meldrim , Brenda D. Kraus , Everett A. McTeer
IPC分类号: H01L29/49 , H01L27/11519 , H01L27/11556 , H01L27/11582 , H01L27/11565
摘要: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
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公开(公告)号:US10700091B2
公开(公告)日:2020-06-30
申请号:US16431527
申请日:2019-06-04
发明人: David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC分类号: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L21/311 , H01L27/11565 , H01L21/768 , H01L27/1157
摘要: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号:US10573661B2
公开(公告)日:2020-02-25
申请号:US16363296
申请日:2019-03-25
IPC分类号: H01L27/11582 , H01L21/3213 , H01L29/10 , H01L21/768 , H01L23/532 , H01L21/285 , H01L23/528 , H01L27/11556 , H01L21/28 , H01L29/49 , H01L27/11519 , H01L27/11565
摘要: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.
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公开(公告)号:US10546848B2
公开(公告)日:2020-01-28
申请号:US16398433
申请日:2019-04-30
发明人: Daniel Billingsley , Everett A. McTeer , Christopher W. Petz , Haoyu Li , John Mark Meldrim , Yongjun Jeff Hu
摘要: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号:US10418554B2
公开(公告)日:2019-09-17
申请号:US16172260
申请日:2018-10-26
摘要: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.
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公开(公告)号:US10355014B1
公开(公告)日:2019-07-16
申请号:US15852989
申请日:2017-12-22
发明人: David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC分类号: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L21/311 , H01L27/11565 , H01L21/768
摘要: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号:US20190067573A1
公开(公告)日:2019-02-28
申请号:US16172260
申请日:2018-10-26
CPC分类号: H01L45/145 , H01L27/2427 , H01L45/04 , H01L45/1253 , H01L45/141 , H01L45/1608
摘要: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.
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