Invention Grant
- Patent Title: System on chip (SOC) with processor and integrated ferroelectric memory
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Application No.: US17726864Application Date: 2022-04-22
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Publication No.: US12125513B2Publication Date: 2024-10-22
- Inventor: Jon D. Trantham , Praveen Viraraghavan , John W. Dykes , Ian J. Gilbert , Sangita Shreedharan Kalarickal , Matthew J. Totin , Mohamad El-Batal , Darshana H. Mehta
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Fremont
- Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee Address: US CA Fremont
- Agency: HOLZER PATEL DRENNAN
- Main IPC: G11C11/22
- IPC: G11C11/22 ; G11C7/10 ; G11C17/12

Abstract:
A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.
Public/Granted literature
- US20220343962A1 SYSTEM ON CHIP (SOC) WITH PROCESSOR AND INTEGRATED FERROELECTRIC MEMORY Public/Granted day:2022-10-27
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