Invention Grant
- Patent Title: Trim/test interface for devices with low pin count or analog or no-connect pins
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Application No.: US18203806Application Date: 2023-05-31
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Publication No.: US12131799B2Publication Date: 2024-10-29
- Inventor: Rajat Chauhan , Divya Kaur , Rishav Gupta
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Charles F. Koch; Frank D. Cimino
- Priority: IN 2041056137 2020.12.23
- Main IPC: G11C7/10
- IPC: G11C7/10 ; H03K19/007

Abstract:
A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.
Public/Granted literature
- US20230343375A1 TRIM/TEST INTERFACE FOR DEVICES WITH LOW PIN COUNT OR ANALOG OR NO-CONNECT PINS Public/Granted day:2023-10-26
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