Invention Grant
- Patent Title: Off-chip memory backed reliable transport connection cache hardware architecture
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Application No.: US17553387Application Date: 2021-12-16
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Publication No.: US12132802B2Publication Date: 2024-10-29
- Inventor: Weihuang Wang , Srinivas Vaduvatha , Xiaoming Wang , Gurushankar Rajamani , Abhishek Agarwal , Jiazhen Zheng , Prashant Chandra
- Applicant: Google LLC
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Lerner David LLP
- Main IPC: H04L67/568
- IPC: H04L67/568 ; G06F16/2455 ; H04L49/00 ; H04L69/326

Abstract:
An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.
Public/Granted literature
- US20230062889A1 Off-Chip Memory Backed Reliable Transport Connection Cache Hardware Architecture Public/Granted day:2023-03-02
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