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公开(公告)号：US20230393987A1
公开(公告)日：2023-12-07
申请号：US17834018
申请日：2022-06-07
申请人： Google LLC
发明人： Jiazhen Zheng , Srinivas Vaduvatha , Hugh McEvoy Walsh , Prashant R. Chandra , Abhishek Agarwal , Weihuang Wang , Weiwei Jiang
IPC分类号： G06F12/0895 , G06F12/0864 , G06F12/121
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/121
摘要： A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.
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公开(公告)号：US20230062889A1
公开(公告)日：2023-03-02
申请号：US17553387
申请日：2021-12-16
申请人： Google LLC
发明人： Weihuang Wang , Srinivas Vaduvatha , Xiaoming Wang , Gurushankar Rajamani , Abhishek Agarwal , Jiazhen Zheng , Prashant Chandra
IPC分类号： H04L67/568 , H04L49/00 , H04L69/326 , G06F16/2455
摘要： An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.
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公开(公告)号：US20240137140A1
公开(公告)日：2024-04-25
申请号：US17969095
申请日：2022-10-18
申请人： Google LLC
IPC分类号： H04J3/06
CPC分类号： H04J3/0667
摘要： Aspects of the disclosure are directed to supporting time synchronization across a datacenter network with greater accuracy. The time synchronization includes both software based and hardware based time synchronization mechanisms to provide more precise time synchronization across various nodes in the datacenter network. The software based mechanism can provide the initial coarse time synchronization while the hardware based mechanism can provide the subsequent finer time synchronization.
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公开(公告)号：US20240064215A1
公开(公告)日：2024-02-22
申请号：US18200074
申请日：2023-05-22
申请人： Google LLC
发明人： Srinivas Vaduvatha , Weiwei Jiang , Prashant Chandra , Opeoluwa Oladipo , Jiazhen Zheng , Hugh McEvoy Walsh , Weihuang Wang , Abhishek Agarwal
CPC分类号： H04L69/04 , H03M7/70 , H03M7/6011
摘要： Compressing connection state information for a network connection including receiving an input bitmap having a sequence of bits describing transmit states and receive states; partitioning the input bitmap into a plurality of equal size blocks; partitioning each of the blocks into a plurality of equal sized sectors; generating a block valid sequence indicating the blocks having at least one bit set; generating, for each block having at least one bit set, a sector information sequence, the sector information sequence indicating, for the corresponding block, the sectors that have at least one bit set and an encoding type for each sector; and generating one or more symbols by encoding each sector that has at least one bit set.
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公开(公告)号：US20230394082A1
公开(公告)日：2023-12-07
申请号：US17833126
申请日：2022-06-06
申请人： Google LLC
发明人： Weiwei Jiang , Srinivas Vaduvatha , Prashant R. Chandra , Jiazhen Zheng , Hugh McEvoy Walsh , Weihuang Wang , Abhishek Agarwal
IPC分类号： G06F3/06 , G06F16/901
CPC分类号： G06F3/0659 , G06F16/9014 , G06F16/9017 , G06F3/0613 , G06F3/0673
摘要： A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.
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公开(公告)号：US20240193093A1
公开(公告)日：2024-06-13
申请号：US18583341
申请日：2024-02-21
申请人： Google LLC
发明人： Jiazhen Zheng , Srinivas Vaduvatha , Hugh McEvoy Walsh , Prashant R. Chandra , Abhishek Agarwal , Weihuang Wang , Weiwei Jiang
IPC分类号： G06F12/0895 , G06F12/0864 , G06F12/121
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/121
摘要： A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.
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公开(公告)号：US11995000B2
公开(公告)日：2024-05-28
申请号：US17834018
申请日：2022-06-07
申请人： Google LLC
发明人： Jiazhen Zheng , Srinivas Vaduvatha , Hugh McEvoy Walsh , Prashant R. Chandra , Abhishek Agarwal , Weihuang Wang , Weiwei Jiang
IPC分类号： G06F12/0895 , G06F12/0864 , G06F12/121
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/121
摘要： A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.
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公开(公告)号：US20240168996A1
公开(公告)日：2024-05-23
申请号：US18423766
申请日：2024-01-26
申请人： Google LLC
发明人： Weiwei Jiang , Srinivas Vaduvatha , Prashant R. Chandra , Jiazhen Zheng , Hugh McEvoy Walsh , Weihuang Wang , Abhishek Agarwal
IPC分类号： G06F16/901 , G06F3/06
CPC分类号： G06F16/9014 , G06F3/0613 , G06F3/0659 , G06F3/0673 , G06F16/9017
摘要： A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.
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公开(公告)号：US20240121320A1
公开(公告)日：2024-04-11
申请号：US17961669
申请日：2022-10-07
申请人： Google LLC
摘要： Aspects of the disclosure are directed to a high performance connection scheduler for reliable transport protocols in data center networking. The connection scheduler can handle enqueue events, dequeue events, and update events. The connection scheduler can include a connection queue, scheduling queue, and quality of service arbiter to support scheduling a large number of connections at a high rate.
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公开(公告)号：US20240111667A1
公开(公告)日：2024-04-04
申请号：US17954540
申请日：2022-09-28
申请人： Google LLC
发明人： Abhishek Agarwal , Srinivas Vaduvatha , Weiwei Jiang , Hugh McEvoy Walsh , Weihuang Wang , Jiazhen Zheng , Ajay Venkatesan
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F12/0292
摘要： Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.
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