Invention Grant
- Patent Title: Droop mitigation for an inter-chiplet interface
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Application No.: US17853812Application Date: 2022-06-29
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Publication No.: US12147366B2Publication Date: 2024-11-19
- Inventor: Michael J. Tresidder , Benjamin Tsien
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Volpe Koenig
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F1/26

Abstract:
Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.
Public/Granted literature
- US20240004821A1 DROOP MITIGATION FOR AN INTER-CHIPLET INTERFACE Public/Granted day:2024-01-04
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