Invention Grant
- Patent Title: High voltage transistor structures
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Application No.: US17815180Application Date: 2022-07-26
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Publication No.: US12148752B2Publication Date: 2024-11-19
- Inventor: Meng-Han Lin , Wen-Tuo Huang , Yong-Shiuan Tsair
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/02 ; H01L21/28 ; H01L21/8234 ; H01L29/40 ; H01L29/423 ; H01L29/49 ; H01L29/66 ; H01L29/78

Abstract:
The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.
Public/Granted literature
- US20220406662A1 High Voltage Transistor Structures Public/Granted day:2022-12-22
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