- Patent Title: Stacked source-drain-gate connection and process for forming such
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Application No.: US18408346Application Date: 2024-01-09
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Publication No.: US12148806B2Publication Date: 2024-11-19
- Inventor: Ehren Mannebach , Aaron Lilak , Hui Jae Yoo , Patrick Morrow , Anh Phan , Willy Rachmady , Cheng-Ying Huang , Gilbert Dewey
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe Williamson & Wyatt, P.C.
- Main IPC: H01L29/417
- IPC: H01L29/417

Abstract:
A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
Public/Granted literature
- US20240145557A1 STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH Public/Granted day:2024-05-02
Information query
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