A memory system includes a memory resource and a smart controller. The memory resource includes semiconductor memory devices, the semiconductor memory devices are divided into a first semiconductor memory and a second semiconductor memory for each of a plurality of channels, and the first semiconductor memory the second semiconductor memory belong to different ranks. The smart controller, connected to the semiconductor memory devices through the channels, controls the semiconductor memory devices by communicating a plurality of hosts through a compute express link (CXL) interface, and each of the plurality of hosts drives at least one virtual machine. The smart controller controls a power mode of the memory resource by managing an idle memory region from among a plurality of memory regions of the plurality of semiconductor memory devices at a rank level without intervention of the plurality of hosts, the plurality of memory regions storing data.