An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.