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    TRANSISTOR WITH A PRIMARY GATE WRAPPING A FLOATING SECONDARY GATE
    2.
    发明公开
    TRANSISTOR WITH A PRIMARY GATE WRAPPING A FLOATING SECONDARY GATE 审中-公开

    公开(公告)号：US20240234533A1

    公开(公告)日：2024-07-11

    申请号：US18152710

    申请日：2023-01-10

    申请人： GlobalFoundries U.S. Inc.

    发明人： Santosh Sharma ,  Shesh Mani Pandey ,  Rajendran Krishnasamy

    IPC分类号： H01L29/47 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

    CPC分类号： H01L29/475 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

    摘要： Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

    Comparator circuits
    7.
    发明授权
    Comparator circuits 有权

    公开(公告)号：US12107585B2

    公开(公告)日：2024-10-01

    申请号：US17956273

    申请日：2022-09-29

    申请人： GlobalFoundries U.S. Inc.

    发明人： Santosh Sharma

    IPC分类号： H03K5/22 ,  H03K17/687

    CPC分类号： H03K5/22 ,  H03K17/6871

    摘要： The present disclosure relates to a circuit and, more particularly, to comparator circuits used with a depletion mode device and methods of operation. The circuit includes: a comparator; a transistor connected to an output of the comparator; and a depletion mode device connected to ground and comprising a control gate connected to the transistor.

    ENHANCEMENT MODE TRANSISTOR WITH A ROBUST GATE AND METHOD
    8.
    发明公开
    ENHANCEMENT MODE TRANSISTOR WITH A ROBUST GATE AND METHOD 审中-公开

    公开(公告)号：US20240204090A1

    公开(公告)日：2024-06-20

    申请号：US18065674

    申请日：2022-12-14

    申请人： GlobalFoundries U.S. Inc.

    发明人： Santosh Sharma ,  Mark D. Levy

    IPC分类号： H01L29/778 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66

    CPC分类号： H01L29/7786 ,  H01L21/32139 ,  H01L29/0642 ,  H01L29/0891 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/66462

    摘要： A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer with a thick portion positioned laterally between thin portions and a gate. The gate includes a semiconductor layer (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion positioned laterally between thin portions. The gate also includes a gate conductor layer on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.

    CIRCUIT FOR CONTROLLING THE SLEW RATE OF A TRANSISTOR
    9.
    发明公开
    CIRCUIT FOR CONTROLLING THE SLEW RATE OF A TRANSISTOR 审中-公开

    公开(公告)号：US20240128958A1

    公开(公告)日：2024-04-18

    申请号：US18045909

    申请日：2022-10-12

    申请人： GlobalFoundries U.S. Inc.

    发明人： Santosh Sharma

    IPC分类号： H03K5/04 ,  H03K17/687

    CPC分类号： H03K5/04 ,  H03K17/6871

    摘要： Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

    SUBSTRATE BIASING FOR BIDIRECTIONAL HIGH ELECTRON MOBILITY TRANSISTOR DEVICE
    10.
    发明公开
    SUBSTRATE BIASING FOR BIDIRECTIONAL HIGH ELECTRON MOBILITY TRANSISTOR DEVICE 审中-公开

    公开(公告)号：US20240072161A1

    公开(公告)日：2024-02-29

    申请号：US17823112

    申请日：2022-08-30

    申请人： GlobalFoundries U.S. Inc.

    发明人： Santosh Sharma

    IPC分类号： H01L29/778 ,  H01L29/20 ,  H03K17/687

    CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H03K17/6871

    摘要： Embodiments of the present disclosure provide a semiconductor device, including: a high electron mobility transistor (HEMT) bidirectional switch including: a first source at a first potential; a second source a second potential different than the first potential; and a substrate; and a biasing circuit, coupled to the first source of the bidirectional switch and the second source of the bidirectional switch, for biasing the substrate at a potential equal to the lower of the first potential of the first source of the bidirectional switch and the second potential of the second source of the bidirectional switch.