An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal is suggested. The apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop. The voltage-controlled oscillator outputs a clock signal that is provided to the phase detector. The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit configured to receive the input signal and to generate two output signals having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.