Invention Grant
- Patent Title: Multi-layer high-k gate dielectric structure
-
Application No.: US18446593Application Date: 2023-08-09
-
Publication No.: US12171091B2Publication Date: 2024-12-17
- Inventor: Chih-Yu Hsu , Jian-Hao Chen , Chia-Wei Chen , Shan-Mei Liao , Hui-Chi Chen , Yu-Chia Liang , Shih-Hao Lin , Kuei-Lun Lin , Kuo-Feng Yu , Feng-Cheng Yang , Yen-Ming Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H10B10/00
- IPC: H10B10/00

Abstract:
A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
Public/Granted literature
- US20230389256A1 MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE Public/Granted day:2023-11-30
Information query