- Patent Title: Bit error rate estimation and classification in NAND flash memory
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Application No.: US18123232Application Date: 2023-03-17
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Publication No.: US12176044B1Publication Date: 2024-12-24
- Inventor: Eyal Nitzan , Avi Steiner , Hanan Weingarten , Yasuhiko Kurosawa
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; H03M13/01 ; H03M13/11 ; H03M13/43

Abstract:
A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.
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