Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.