公开(公告)号：US11610639B2

公开(公告)日：2023-03-21

申请号：US17336378

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhyang Park ,  Jinyoung Kim ,  Jisang Lee ,  Sehwan Park ,  Ilhan Park

IPC: G11C16/26 ,  G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C16/04 ,  G11C29/12

Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.

公开(公告)号：US12230329B2

公开(公告)日：2025-02-18

申请号：US17953003

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhyang Park ,  Joonsuc Jang ,  Se Hwan Park ,  Ji-Sang Lee

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/34

Abstract: A flash memory device includes a memory cell array connected with word lines and control logic that performs threshold voltage compensation on the word lines through a data recover read operation. When a word line on which programming is performed after a selected word line is a dummy word line, the control logic performs the threshold voltage compensation on the selected word line based on a result of a data recover read operation of a word line on which programming is performed before the selected word line. When a next word line on which programming is performed after a selected word line is a dummy word line, the control logic performs threshold voltage compensation on the selected word line based on a result of performing the data recover read operation on a previous word line on which programming is performed before the selected word line.

公开(公告)号：US12176046B2

公开(公告)日：2024-12-24

申请号：US17955858

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Lee ,  Sang-Wan Nam ,  Sang-Won Park ,  Jiho Cho ,  Eunhyang Park

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.