Invention Grant
- Patent Title: Heterogeneous nested interposer package for IC chips
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Application No.: US18397915Application Date: 2023-12-27
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Publication No.: US12199048B2Publication Date: 2025-01-14
- Inventor: Debendra Mallik , Ravindranath Mahajan , Robert Sankman , Shawna Liff , Srinivas Pietambaram , Bharat Penmecha
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/538

Abstract:
Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
Public/Granted literature
- US20240128205A1 HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPS Public/Granted day:2024-04-18
Information query
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