Invention Grant
- Patent Title: Biased amplifier
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Application No.: US18298594Application Date: 2023-04-11
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Publication No.: US12218641B2Publication Date: 2025-02-04
- Inventor: Sudheer Prasad
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Priority: IN201741036697 20171016
- Main IPC: H03F3/45
- IPC: H03F3/45 ; H03F3/16

Abstract:
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
Public/Granted literature
- US20230275550A1 BIASED AMPLIFIER Public/Granted day:2023-08-31
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