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公开(公告)号：US10804887B1
公开(公告)日：2020-10-13
申请号：US16584529
申请日：2019-09-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudheer Prasad
IPC: H03K5/08 , H03K17/082 , H03K17/16 , H01L27/02
Abstract: A system includes: 1) a buffer circuit; 2) circuitry coupled to an input of the buffer circuit; 3) a load coupled to an output of the buffer circuit; and 4) a clamp circuit coupled between an input of the buffer circuit and the output of the buffer circuit. The clamp circuit includes: 1) a bipolar junction transistor (BJT); 2) a first resistor with a first end coupled to a base terminal of the BJT and with a second end coupled to a collector terminal of the BJT; and 3) a second resistor with a first end coupled to the collector terminal of the BJT and with a second end coupled to the input of the buffer circuit. The second resistor is between an output of the circuitry and the input of the buffer circuit.
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公开(公告)号：US10587235B2
公开(公告)日：2020-03-10
申请号：US15912477
申请日：2018-03-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudheer Prasad
Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
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公开(公告)号：US10361695B2
公开(公告)日：2019-07-23
申请号：US16001518
申请日：2018-06-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ankur Chauhan , Sudheer Prasad , Md. Abidur Rahman , Subrato Roy
IPC: H03K3/00 , H03K17/082 , G01R19/00 , H01L23/525 , H03K17/687
Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
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公开(公告)号：US20180123578A1
公开(公告)日：2018-05-03
申请号：US15341205
申请日：2016-11-02
Applicant: Texas Instruments Incorporated
Inventor： Ankur Chauhan , Sudheer Prasad , Md. Abidur Rahman , Subrato Roy
IPC: H03K17/082 , H03K17/687 , H01L23/525 , G01R19/00
CPC classification number: H03K17/0822 , G01R19/0092 , H01L23/5256 , H03K17/687 , H03K2217/0027 , H03K2217/0054
Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
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公开(公告)号：US20170257088A1
公开(公告)日：2017-09-07
申请号：US15386252
申请日：2016-12-21
Applicant: Texas Instruments Incorporated
Inventor： Xiaoju Wu , Rajesh Keloth , Sudheer Prasad
IPC: H03K17/08 , H01L29/417 , H01L29/78 , H01L27/02 , H01L29/06
CPC classification number: H03K17/08 , H01L27/0262 , H01L29/063 , H01L29/41775 , H01L29/7835 , H03K17/08142 , H03K17/6874 , H03K2217/0018
Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.
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Patent Agency Ranking
公开(公告)号：US11025216B2
公开(公告)日：2021-06-01
申请号：US16804253
申请日：2020-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudheer Prasad
Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
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公开(公告)号：US10014851B2
公开(公告)日：2018-07-03
申请号：US15341205
申请日：2016-11-02
Applicant: Texas Instruments Incorporated
Inventor： Ankur Chauhan , Sudheer Prasad , Md. Abidur Rahman , Subrato Roy
IPC: H03K17/00 , H03K17/082 , H03K17/687 , H01L23/525 , G01R19/00
CPC classification number: H03K17/0822 , G01R19/0092 , H01L23/5256 , H03K17/687 , H03K2217/0027 , H03K2217/0054
Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
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公开(公告)号：US09838003B1
公开(公告)日：2017-12-05
申请号：US15210672
申请日：2016-07-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudheer Prasad
IPC: H01H37/76 , H01H85/00 , H03K17/22 , H01L23/525 , H03K5/08
CPC classification number: H03K17/22 , G05F1/468 , H01L23/5256 , H02H9/001 , H02M1/36 , H02M2001/0045 , H03K5/08 , H03K17/223
Abstract: A detection circuit includes a first transistor coupled to a gate of a high power transistor, a second transistor whose source is coupled to a drain of the first transistor, a first voltage divider coupled to a source of the first transistor, and a second voltage divider coupled to the source of the second transistor. The first transistor is configured to generate a first transistor output voltage representative of a gate voltage of the high power transistor shifted based on a first gate-to-source voltage of the first transistor. The second transistor is configured to generate a second gate-to-source voltage substantially equal to the first gate-to-source voltage. The first divider is configured to divide the first transistor output voltage by a first factor. The second divider is configured to divide the second gate-to-source voltage by a second factor correlated with the first factor.
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公开(公告)号：US09641142B2
公开(公告)日：2017-05-02
申请号：US14965588
申请日：2015-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudheer Prasad
CPC classification number: H03F3/393 , H03F1/086 , H03F3/45475 , H03F3/45977 , H03F2200/252 , H03F2200/267 , H03F2200/271 , H03F2200/297 , H03F2200/471 , H03F2203/45151 , H03F2203/45212 , H03F2203/45264 , H03F2203/45288
Abstract: One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage.
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公开(公告)号：US12218641B2
公开(公告)日：2025-02-04
申请号：US18298594
申请日：2023-04-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sudheer Prasad
Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
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