An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.