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    Voltage providing circuit
    2.
    发明授权
    Voltage providing circuit 有权
    电压提供电路

    公开(公告)号：US09104214B2

    公开(公告)日：2015-08-11

    申请号：US13779020

    申请日：2013-02-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： I-Han Huang ,  Chia-En Huang ,  Chih-Chieh Chiu ,  Fu-An Wu ,  Chun-Jiun Dai ,  Hong-Chen Cheng ,  Jung-Ping Yang ,  Cheng Hung Lee

    IPC: G05F3/02 ,  G05F1/10 ,  G05F3/08

    CPC classification number: G05F3/242 ,  G05F3/08 ,  G05F3/24 ,  G11C5/148 ,  H03K19/00361

    Abstract: A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage.

    Abstract translation: 电压提供电路包括第一电路，与第一电路耦合的第二电路以及与第二电路耦合的第三电路。 第一电路被配置为接收第一输入信号并产生第一输出信号。 第二电路被配置为接收第一输入信号和第一输出信号作为输入并产生第二输出信号。 第三电路被配置为接收第二输出信号并产生输出电压。

    Wake up bias circuit and method of using the same
    4.
    发明授权
    Wake up bias circuit and method of using the same 有权
    唤醒偏置电路及其使用方法

    公开(公告)号：US09164522B2

    公开(公告)日：2015-10-20

    申请号：US14051681

    申请日：2013-10-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Jung-Ping Yang ,  I-Han Huang ,  Chia-En Huang ,  Fu-An Wu ,  Chih-Chieh Chiu

    IPC: H03B1/00 ,  H03K5/00 ,  H04B1/10 ,  G05F1/46

    CPC classification number: G05F1/46 ,  H03K17/163 ,  H03K17/164

    Abstract: A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.

    Abstract translation: 唤醒电路包括被配置为接收睡眠信号并产生多个偏置控制信号的偏置信号控制块。 唤醒电路还包括偏置电源模块，其被配置为接收多个偏置控制信号的每个偏置控制信号并产生报头偏置信号。 偏置电源块包括第一偏置级，其被配置为接收多个偏置控制信号的第一偏置控制信号，并且将该标题偏置信号控制为等于第一电压。 偏置电源模块进一步包括第二偏置级，其被配置为接收多个偏置控制信号的第二偏置控制信号，并且控制标题偏置信号等于与第一电压不同的第二电压。 唤醒电路还包括被配置为接收标题偏置信号的接头，并且基于报头偏置信号选择性地将电源电压连接到负载。

    Three-dimensional (3-D) write assist scheme for memory cells
    5.
    发明授权
    Three-dimensional (3-D) write assist scheme for memory cells 有权

    公开(公告)号：US10777244B2

    公开(公告)日：2020-09-15

    申请号：US16205534

    申请日：2018-11-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chih-Chieh Chiu ,  Chia-En Huang ,  Fu-An Wu ,  I-Han Huang ,  Jung-Ping Yang

    IPC: G11C11/419 ,  G11C8/10 ,  G11C7/02 ,  G11C8/14 ,  G11C11/418

    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.

    Circuit for memory write data operation
    7.
    发明授权
    Circuit for memory write data operation 有权
    存储器写数据操作电路

    公开(公告)号：US09117510B2

    公开(公告)日：2015-08-25

    申请号：US13804231

    申请日：2013-03-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Jung-Ping Yang ,  Cheng Hung Lee ,  Chia-En Huang ,  Fu-An Wu ,  Chih-Chieh Chiu

    IPC: G11C7/00 ,  G11C7/22 ,  G11C11/419

    CPC classification number: G11C7/22 ,  G11C11/419 ,  G11C2207/2227

    Abstract: A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage.

    Abstract translation: 用于改善SRAM的写操作的脉冲动态LCV电路。 脉冲动态LCV电路包括具有多个可选择的降低的电源电压的电压调节电路和具有多个可选择的逻辑状态转换时序的定时调整电路，用于可调节地控制从所选择的降低的电源电压向标称的转换的电压和定时 电源电压。 电压调节电路具有多个可选择的晶体管，当单独选择时具有累积效应以进一步拉低降低的电源电压。 定时调整电路具有多个可选择的多路复用器，当单独选择延迟电压转换时，累积效应将延迟从提供给SRAM的电压从降低的电源电压恢复到额定电源电压。

    Three-dimensional (3-D) write assist scheme for memory cells
    8.
    发明授权
    Three-dimensional (3-D) write assist scheme for memory cells 有权

    公开(公告)号：US12237050B2

    公开(公告)日：2025-02-25

    申请号：US17859545

    申请日：2022-07-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chih-Chieh Chiu ,  Chia-En Huang ,  Fu-An Wu ,  I-Han Huang ,  Jung-Ping Yang

    IPC: G11C11/419 ,  G11C7/02 ,  G11C8/10 ,  G11C8/14 ,  G11C11/418

    Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

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