Invention Application
US20010034819A1 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
有权
用于交错存储器和负载脉冲发生器电路的交错数据路径和输出管理架构,用于输出读取的数据
- Patent Title: Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
- Patent Title (中): 用于交错存储器和负载脉冲发生器电路的交错数据路径和输出管理架构,用于输出读取的数据
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Application No.: US09774542Application Date: 2001-01-31
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Publication No.: US20010034819A1Publication Date: 2001-10-25
- Inventor: Salvatore Nicosia , Francesco Tomaiuolo , Fabrizio Campanale , Luca Giuseppe De Ambroggi , Promod Kumar
- Applicant: STMicroelectronics S.r.I.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.I.
- Current Assignee: STMicroelectronics S.r.I.
- Current Assignee Address: IT Agrate Brianza
- Priority: EP00830068.3 20000131; EP00830291.1 20000417
- Main IPC: G06F012/00
- IPC: G06F012/00

Abstract:
An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.
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