公开(公告)号：US20010034819A1

公开(公告)日：2001-10-25

申请号：US09774542

申请日：2001-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC: G06F012/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Abstract translation: 具有交错数据路径的交错存储器包括被分成第一存储单元组和第二存储单元组的存储器单元的阵列，分别耦合到第一和第二存储单元组的读出放大器的第一和第二阵列，以及 分别耦合到第一和第二读出放大器阵列的第一和第二读取寄存器。 控制和定时电路连接到第一和第二读出放大器阵列，并且具有用于接收外部产生的命令信号的输入，以及用于提供路径选择信号和控制信号的输出。 第三寄存器连接到第一和第二读取寄存器，并且具有用于根据路径选择信号接收其中的读取数据的输入。 一个通道阵列连接到第三寄存器，并被控制信号共同控制，以便将存储在第三寄存器中的读取数据传送到输出缓冲器阵列。

公开(公告)号：US20010033245A1

公开(公告)日：2001-10-25

申请号：US09773300

申请日：2001-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar ,  Luigi Pascucci

IPC: H03M001/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Abstract translation: 适用于更广泛应用的多用途存储器件，无论是要求以随机存取（如在标准存储器中）或具有顺序或突发型访问的同步顺序模式的异步模式中的数据读取，都能够识别 访问模式和微处理器当前需要的读取模式。 存储器设备将其内部电路作为这种识别的功能进行自我调整，以便以所请求的模式读取数据，而不需要使用额外的外部控制信号和/或暗示相对于访问时间和读取时间的惩罚 对于相同的制造技术和现有技术设计的那些，可以通过专门为一种或另一种操作模式设计的存储器件来实现。