Invention Application
- Patent Title: Solderless electronics packaging and methods of manufacture
- Patent Title (中): 无焊电子封装及制造方法
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Application No.: US09726629Application Date: 2000-11-30
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Publication No.: US20020065965A1Publication Date: 2002-05-30
- Inventor: Ajit V. Sathe , Paul H. Wermer
- Applicant: Intel Corporation
- Applicant Address: null
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: null
- Main IPC: G06F013/00
- IPC: G06F013/00

Abstract:
To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.
Public/Granted literature
- US06840777B2 Solderless electronics packaging Public/Granted day:2005-01-11
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