公开(公告)号：US20030227077A1

公开(公告)日：2003-12-11

申请号：US10424383

申请日：2003-04-28

Applicant: Intel Corporation

Inventor： Steven Towle ,  Paul H. Wermer

IPC: H01L023/02

CPC classification number: H01L21/568 ,  H01L23/142 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4614 ,  H01L2924/00

Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.

公开(公告)号：US20030011960A1

公开(公告)日：2003-01-16

申请号：US10242177

申请日：2002-09-12

Applicant: Intel Corporation

Inventor： Paul A. Koning ,  Paul H. Wermer

IPC: H01G004/06 ,  H01G004/20

CPC classification number: C07D487/22 ,  B82Y10/00 ,  B82Y30/00 ,  C09B47/08 ,  H01B3/30 ,  H01G4/18 ,  H05K1/162 ,  H05K2201/0323 ,  H05K2203/121

Abstract: The present invention includes a dielectric. The dielectric comprises a polymer that has a high dielectric constant. The polymer comprises polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.

公开(公告)号：US20040238942A1

公开(公告)日：2004-12-02

申请号：US10884644

申请日：2004-07-02

Applicant: Intel Corporation

Inventor： Kishore K. Chakravorty ,  Paul H. Wermer ,  David G. Figueroa ,  Debabrata Gupta

IPC: H01L023/48 ,  H01L029/40

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/141 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

公开(公告)号：US20030205406A1

公开(公告)日：2003-11-06

申请号：US10419400

申请日：2003-04-21

Applicant: Intel Corporation

Inventor： Paul H. Wermer ,  Brian Kaiser

IPC: H05K001/16

CPC classification number: H05K1/115 ,  H05K1/162 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2203/135

Abstract: The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.

公开(公告)号：US20020105774A1

公开(公告)日：2002-08-08

申请号：US09733484

申请日：2000-12-08

Applicant: Intel Corporation

Inventor： Paul H. Wermer ,  Brian Kaiser

IPC: H01G004/06

CPC classification number: H05K1/115 ,  H05K1/162 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2203/135

Abstract: The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.

Abstract translation: 本发明包括使用电涂覆工艺在有机衬底中的通孔通孔结构的导电层之间形成薄的，共形的，高完整性的电介质涂层，以减少导电层之间的环路电感。 使用高介电常数材料如有机聚合物和有机聚合物混合物形成电介质涂层。 本发明还包括在基本平坦的基板材料和嵌入式电容器之间的导电层之间形成薄的电介质涂层，以减小环路电感。

公开(公告)号：US20020065965A1

公开(公告)日：2002-05-30

申请号：US09726629

申请日：2000-11-30

Applicant: Intel Corporation

Inventor： Ajit V. Sathe ,  Paul H. Wermer

IPC: G06F013/00

CPC classification number: H01L23/10 ,  H01L23/055 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81101 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01R12/57 ,  H05K3/325 ,  H05K7/1061 ,  H05K13/046 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2224/05599

Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

Abstract translation: 为了降低电子封装的厚度或堆叠高度，封装在集成电路（IC）封装和诸如印刷电路板（PCB）的基板之间包括无焊压缩连接器。 在一个实施例中，使用平面栅格阵列布置将IC封装安装在基板上。 使用无焊压缩连接器将IC封装和衬底上的对应区域耦合。 压缩连接器包括多个导电元件，诸如可压缩按钮触点，以及有孔支撑件，其将按钮触点与IC封装和基板上的对应的平台对准。 在另一个实施例中，连接器包括嵌入薄塑料片中的导电针。 在另一实施例中，连接器包括具有导电晶体的微晶膜。 在另一实施例中，压缩连接器用于IC封装内以将IC耦合到IC封装基板。 还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。