Invention Application
- Patent Title: Semiconductor structure exhibiting reduced leakage current and method of fabricating same
- Patent Title (中): 具有减小漏电流的半导体结构及其制造方法
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Application No.: US10207210Application Date: 2002-07-30
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Publication No.: US20020187600A1Publication Date: 2002-12-12
- Inventor: Zhiyi Yu , Ravindranath Droopad
- Applicant: MOTOROLA, INC.
- Applicant Address: IL Schaumburg
- Assignee: MOTOROLA, INC.
- Current Assignee: MOTOROLA, INC.
- Current Assignee Address: IL Schaumburg
- Main IPC: H01L021/8238
- IPC: H01L021/8238

Abstract:
A semiconductor structure exhibiting reduced leakage current is formed of a monocrystalline substrate (101) and a strained-layer heterostructure (105). The strained-layer heterostructure has a first layer (102) formed of a first monocrystalline oxide material having a first lattice constant and a second layer (104) formed of a second monocrystalline oxide material overlying the first layer and having a second lattice constant. The second lattice constant is different from the first lattice constant. The second layer creates strain within the oxide material layers, at the interface between the first and second oxide material layers of the heterostructure, and at the interface of the substrate and the first layer, which changes the energy band offset at the interface of the substrate and the first layer.
Public/Granted literature
- US07045815B2 Semiconductor structure exhibiting reduced leakage current and method of fabricating same Public/Granted day:2006-05-16
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