Invention Application
- Patent Title: Electronic package having multiple-zone interconnects and methods of manufacture
- Patent Title (中): 具有多区域互连的电子封装和制造方法
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Application No.: US10004002Application Date: 2001-11-30
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Publication No.: US20030103338A1Publication Date: 2003-06-05
- Inventor: Gilroy J. Vandentop , Yuan-Liang Li
- Applicant: Intel Corporation
- Applicant Address: null
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: null
- Main IPC: H05K007/10
- IPC: H05K007/10 ; H05K007/12

Abstract:
To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.
Public/Granted literature
- US06717066B2 Electronic packages having multiple-zone interconnects and methods of manufacture Public/Granted day:2004-04-06
Information query