公开(公告)号：US20040188811A1

公开(公告)日：2004-09-30

申请号：US10396945

申请日：2003-03-24

Applicant: Intel Corporation

Inventor： Gilroy J. Vandentop ,  Rajendran Nair

IPC: H01L021/44

CPC classification number: H01L25/18 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2224/0401

Abstract: An apparatus and system, as well as methods for providing them, may include a die having a core circuit electrically coupled to a power converter included in an active substrate.

Abstract translation: 装置和系统以及用于提供它们的方法可以包括具有电耦合到包括在有源基板中的功率转换器的核心电路的管芯。

公开(公告)号：US20030103338A1

公开(公告)日：2003-06-05

申请号：US10004002

申请日：2001-11-30

Applicant: Intel Corporation

Inventor： Gilroy J. Vandentop ,  Yuan-Liang Li

IPC: H05K007/10 ,  H05K007/12

CPC classification number: H01L24/73 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10659 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00

Abstract: To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.

Abstract translation: 为了适应由封装的或未封装的裸片和衬底的不同热膨胀系数（CTE）产生的热应力，封装包含两个或多个不同的互连区域。 位于模具的中心区域中的第一互连区域采用相对较硬的互连结构。 位于模具周边附近的第二互连区采用相对顺应的互连结构。 位于第一和第二互连区之间并具有与第一和第二区之间的顺应性质量的互连结构的附加互连区可以任选地被采用。 在一个实施例中，在第一互连区域中使用提供低电阻的焊接连接，并且在第二互连区域中使用诸如纳米脉冲的顺应连接。 还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。