发明申请
- 专利标题: Patterned SOI regions on semiconductor chips
- 专利标题(中): 半导体芯片上的图案化SOI区域
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申请号: US09975435申请日: 2001-10-11
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公开(公告)号: US20030104681A1公开(公告)日: 2003-06-05
- 发明人: Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
- 主分类号: H01L021/331
- IPC分类号: H01L021/331 ; H01L021/8222 ; H01L027/01 ; H01L027/12 ; H01L031/0392 ; H01L021/322 ; C30B001/00 ; H01L021/20 ; H01L021/36
摘要:
A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.
公开/授权文献
- US06756257B2 Patterned SOI regions on semiconductor chips 公开/授权日:2004-06-29
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