公开(公告)号：US20040203195A1

公开(公告)日：2004-10-14

申请号：US10833754

申请日：2004-04-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takatoshi Tsujimura ,  Osamu Tokuhiro ,  Mitsuo Morooka ,  Takashi Miyamoto

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L021/336 ,  H01L021/8234 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC分类号： H01L29/78696 ,  H01L29/66765 ,  H01L29/78669

摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。

公开(公告)号：US20040185600A1

公开(公告)日：2004-09-23

申请号：US10392983

申请日：2003-03-21

申请人： International Business Machines Corporation

发明人： Cherie Renee Kagan ,  Richard Martel

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L027/12 ,  H01L027/01

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  B82Y30/00 ,  H01L51/0036 ,  H01L51/0052 ,  H01L51/0062 ,  H01L51/0078 ,  H01L51/0545 ,  Y10S977/709 ,  Y10S977/731

摘要： An electronic device includes a source region and a drain region, a self-assembled monolayer disposed adjacent to the source region and the drain region, the self-assembled monolayer including at least one conjugated molecule, and a conductive substrate disposed adjacent to the self-assembled monolayer.

摘要翻译： 电子器件包括源极区和漏极区，邻近源极区和漏极区设置的自组装单层，包含至少一个共轭分子的自组装单层和邻近自组装的导电衬底， 组装单层。

公开(公告)号：US20040104434A1

公开(公告)日：2004-06-03

申请号：US10714700

申请日：2003-11-17

申请人： Prime View International Co., Ltd.

发明人： Wen-Jian Lin

IPC分类号： G02F001/136 ,  H01L021/00 ,  H01L027/12 ,  H01L031/0392

CPC分类号： G02F1/133553

摘要： There is provided a reflection type/transflection type thin film transistor liquid crystal display, including an insulating substrate, a thin film transistor formed on the insulating substrate, a transparent electrode made of indium-tin-oxide formed on the thin film transistor and electrically contacted with a source region and a drain region of the thin film transistor, and a curved conducting structure with an inclination of 3 to 20 degrees formed on the transparent electrode.

摘要翻译： 提供一种反射型/转换型薄膜晶体管液晶显示器，包括绝缘基板，形成在绝缘基板上的薄膜晶体管，形成在薄膜晶体管上的由氧化铟锡形成的透明电极，并电接触 具有薄膜晶体管的源极区域和漏极区域，以及在透明电极上形成具有3至20度倾斜度的弯曲导电结构。

公开(公告)号：US20040094797A1

公开(公告)日：2004-05-20

申请号：US10414654

申请日：2003-04-16

发明人： Il-Yong Park ,  Sang-Gi Kim ,  Byoung-Gon Yu ,  Jong-Dae Kim ,  Tae-Moon Roh ,  Dae-Woo Lee ,  Yil-Suk Yang

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L027/12 ,  H01L027/01

CPC分类号： H01L29/66621 ,  H01L21/2255 ,  H01L29/66553 ,  H01L29/7834

摘要： The MOS transistor of the present invention is manufactured by a conventional complementary MOS transistor technology. In the manufacturing method of the MOS transistor having nanometer dimensions, a gate having dimensions at a nanometer scale can be formed through control of the width of spacers instead of with a specific lithography technology. The doped spacers are used for forming source/drain extension regions having an ultra-shallow junction, thereby avoiding damage on the substrate caused by ion implantation. In addition, a dopant is diffused from the doped space into a semiconductor substrate through annealing to form the source/drain extension regions having an ultra-shallow junction.

摘要翻译： 本发明的MOS晶体管通过常规的互补MOS晶体管技术制造。 在具有纳米尺寸的MOS晶体管的制造方法中，可以通过控制间隔物的宽度而不是使用特定的光刻技术来形成具有纳米级尺寸的栅极。 掺杂的间隔物用于形成具有超浅结的源极/漏极延伸区域，从而避免由离子注入引起的对衬底的损伤。 此外，通过退火将掺杂剂从掺杂空间扩散到半导体衬底中以形成具有超浅结的源极/漏极延伸区域。

公开(公告)号：US20040079995A1

公开(公告)日：2004-04-29

申请号：US10687333

申请日：2003-10-16

发明人： Andres Bryant ,  Peter E. Cottrell ,  John J. Ellis-Monaghan ,  Robert J. Gauthier JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  Fariborz Assaderaghi

IPC分类号： H01L021/00 ,  H01L027/12

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.

摘要翻译： 公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。 在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。 在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。 在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。 通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

公开(公告)号：US20040061172A1

公开(公告)日：2004-04-01

申请号：US10262190

申请日：2002-10-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Byeongju Park

IPC分类号： H01L027/12

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

摘要翻译： 公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。 在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法（例如气相掺杂或等离子体掺杂）时。 所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。 提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。

公开(公告)号：US20040051141A1

公开(公告)日：2004-03-18

申请号：US10602065

申请日：2003-06-24

申请人： CAMBRIDGE SEMICONDUCTOR LIMITED

发明人： Florin Udrea

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/0634 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/861

摘要： A lateral semiconductor device (10) has a semiconductor layer (15) on an insulating substrate (16). The semiconductor layer (15) has a first region (12) of a first conduction type and a second region (13) of a second conduction type with a drift region (14) therebetween. The drift region (14) is provided by a third region (14null) of the first conduction type and a fourth region (14null) of the second conduction type. The third and fourth (drift) regions (14null,14null) are so arranged that when a reverse voltage bias is applied across the first and second regions (12,13) of the semiconductor layer (15), the third region (14null) has locally in the proximity of the first region (12) an excess of impurity charge relative to the fourth region (14null), and the fourth region (14null) has locally in the proximity of the second region (13) an excess of impurity charge relative to the third region (14null), and the total volume charge in the third region (14null) is substantially equal to the total volume charge in the fourth region (14null).

摘要翻译： 横向半导体器件（10）在绝缘基板（16）上具有半导体层（15）。 半导体层（15）具有第一导电类型的第一区域（12）和第二导电类型的第二区域（13），其间具有漂移区域（14）。 漂移区域（14）由第一导电类型的第三区域（14“）和第二导电类型的第四区域（14'）提供。 第三和第四（漂移）区域（14“，14”）被布置成使得当跨越半导体层（15）的第一和第二区域（12,13）施加反向电压偏压时，第三区域 14“）在第一区域（12）附近具有相对于第四区域（14'）过多的杂质电荷，并且第四区域（14'）局部地位于第二区域（13）附近 ）相对于第三区域（14“）的过量的杂质电荷，并且第三区域（14”）中的总体积电荷基本上等于第四区域（14'）中的总体积电荷。

公开(公告)号：US20040046207A1

公开(公告)日：2004-03-11

申请号：US10235147

申请日：2002-09-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Robert H. Dennard ,  Wilfried E. Haensch ,  Hussein I. Hanafi

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78648

摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

摘要翻译： 提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。 如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。 在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

公开(公告)号：US20040026740A1

公开(公告)日：2004-02-12

申请号：US10633754

申请日：2003-08-04

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Ritsuko Kawasaki ,  Hidehito Kitakado ,  Kenji Kasahara ,  Shunpei Yamazaki

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L27/1214 ,  G02F1/13454 ,  H01L27/3244 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78633 ,  H01L29/78636 ,  H01L29/78645

摘要： To improve the operation characteristic and reliability of a semiconductor device by optimizing the structure of bottom gate type or inverted stagger type TFTs arranged in circuits of the semiconductor device in accordance with the function of the respective circuits. At least LDD regions that overlap with a gate electrode are formed in an N channel type TFT of a driving circuit, and LDD regions that do not overlap with the gate electrode are formed in an N channel type TFT of a pixel matrix circuit. The concentration of the two kinds of LDD regions is differently set from each other, to thereby obtain the optimal circuit operation.

摘要翻译： 通过根据各个电路的功能优化设置在半导体器件的电路中的底栅型或倒置交错型TFT的结构来提高半导体器件的操作特性和可靠性。 至少与栅电极重叠的LDD区域形成在驱动电路的N沟道型TFT中，并且在像素矩阵电路的N沟道型TFT中形成与栅电极不重叠的LDD区域。 两种LDD区域的浓度彼此不同，从而获得最佳电路操作。

公开(公告)号：US20030201495A1

公开(公告)日：2003-10-30

申请号：US10419428

申请日：2003-04-21

发明人： Thomas Doderer ,  Wei Hwang ,  Chang C. Tsuei

IPC分类号： H01L027/01 ,  H01L027/12

CPC分类号： H01L49/003 ,  H01L27/12

摘要： A microelectronic device includes a gate layer adapted to receive an input voltage. An insulating layer is formed on the gate layer, and a conductive channel layer is formed on the insulating layer and carries current between a source and a drain. The conductive channel layer is adapted to provide a dual channel. The dual channel includes both a p-channel and an n-channel wherein one of the p-channel and the n-channel are selectively enabled responsive to the input voltage polarity. A method for forming the device and applications are also disclosed and claimed.

摘要翻译： 微电子器件包括适于接收输入电压的栅极层。 在栅极层上形成绝缘层，在绝缘层上形成导电沟道层，并在源极和漏极之间传导电流。 导电沟道层适于提供双通道。 双通道包括p沟道和n沟道，其中p沟道和n沟道之一响应于输入电压极性而选择性地使能。 还公开并要求保护用于形成装置和应用的方法。