The invention is directed to a fabrication method of copper interconnects using dual damascene processing. Using silicon to provide an active surface, palladium can be selectively deposited on silicon by immersion plating technique. After palladium deposition (about 1000 A thick), either a layer of cobalt phosphorus or alloy cobalt/nickel phosphorus or nickel phosphorus is deposited on palladium layer using electroless plating technique. This cobalt/phosphorus, cobalt nickel phosphorus alloy, or nickel phosphorus layer serves as a copper diffusion barrier. Via and trench are filled up by copper from electroless copper plating method and CMP is used to remove excess copper and planarize/polish the copper/dielectric surface.