公开(公告)号：US20040266164A1

公开(公告)日：2004-12-30

申请号：US10874237

申请日：2004-06-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chao-Fu Weng

IPC: H01L021/44

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: A bumping process mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming a patterned adhesive layer over the bonding pads, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer and reflowing the bumps.

Abstract translation: 凸起工艺主要包括以下步骤：提供具有多个焊盘的晶片，在焊盘上形成图案化的粘合剂层，在图案化的粘合剂层和晶片的表面上形成阻挡层和润湿层， 阻挡层和不覆盖图案化粘合剂层的润湿层，在图案化的润湿层上形成多个凸起并回流凸块。

公开(公告)号：US20040266161A1

公开(公告)日：2004-12-30

申请号：US10753316

申请日：2004-01-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ching-Fu Horng

IPC: H01L021/44 ,  H01L021/4763 ,  H01L021/48

CPC classification number: H01L24/11 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

Abstract: A method of forming a plurality of bumps over a wafer mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming an adhesive layer on the surface of the wafer to cover the bonding pads, patterning the adhesive layer to expose the bonding pads to form a patterned adhesive layer, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer, and reflowing the bumps.

Abstract translation: 在晶片上形成多个凸块的方法主要包括以下步骤：提供具有多个接合焊盘的晶片，在晶片的表面上形成粘合剂层以覆盖接合焊盘，图案化粘合剂层以暴露键合 衬垫以形成图案化的粘合剂层，在图案化的粘合剂层和晶片的表面上形成阻挡层和润湿层，去除不覆盖图案化的粘合剂层的阻挡层和润湿层，在其上形成多个凸块 图案化润湿层，并且回流凸块。

公开(公告)号：US20040266160A1

公开(公告)日：2004-12-30

申请号：US10709940

申请日：2004-06-08

Inventor： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L24/13 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract translation: 衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和 焊料凸块形成在UBM层上。

公开(公告)号：US20040266081A1

公开(公告)日：2004-12-30

申请号：US10832080

申请日：2004-04-26

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Chang-Sub Lee

IPC: H01L021/336 ,  H01L021/8234 ,  H01L021/3205 ,  H01L021/4763 ,  H01L021/44

CPC classification number: H01L29/66621 ,  H01L29/66537 ,  H01L29/66553

Abstract: A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.

Abstract translation: 形成场效应晶体管的方法可以包括在半导体衬底的表面上形成掺杂层，并且在半导体衬底的表面上形成通过掺杂层的沟槽，同时保持掺杂层在槽的相对侧上的部分 。 可以在沟槽的表面上形成栅极绝缘层，并且可以在沟槽中的栅极绝缘层上形成栅电极。

公开(公告)号：US20040266070A1

公开(公告)日：2004-12-30

申请号：US10612282

申请日：2003-06-30

Inventor： Charan K. Gurumurthy ,  Hamid Azimi ,  Arthur K. Lin

IPC: H01L021/44

CPC classification number: H05K3/243 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2203/1572 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.

Abstract translation: 一种形成可适于附接到一个或多个电子部件的集成电路基板的方法。 该方法包括将抗蚀剂涂覆在基板的背面，该基板在基板的正面和背面包括图案化的导电层。 该方法还包括从衬底的前侧去除图案化的导电层的一部分，以在衬底的正面上形成焊盘和互连，并将另一个抗蚀剂施加到衬底的正面。 该方法还包括在每个抗蚀剂中形成图案，其暴露衬底的正面和背面上的焊盘并将电解镍施加到衬底上的焊盘。

公开(公告)号：US20040266068A1

公开(公告)日：2004-12-30

申请号：US10731177

申请日：2003-12-09

Inventor： J. Christopher Matayabas JR. ,  Constance L. Gettinger

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L23/3121 ,  H01L23/3135 ,  H01L23/3737 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least a portion of the die and a thermally conductive portion overmolded on the die and the electrically insulating portion. Also disclosed is a process comprising providing a die connected to a substrate by a plurality of wires, encapsulating the wires and at least a portion of the die in an electrically insulating material, and encapsulating the die, the wires and the electrically insulating material in a thermally conductive material. Other embodiments are disclosed and claimed.

Abstract translation: 本说明书公开了一种装置，其包括：安装在基板上的管芯，该管芯通过多根导线与基板连接;模具盖封装该芯片和该多根金属丝，该模具盖包括电绝缘部分， 以及模具的至少一部分和在模具和电绝缘部分上包覆模制的导热部分。 还公开了一种方法，其包括通过多根导线提供连接到衬底的管芯，将电线和芯片的至少一部分封装在电绝缘材料中，并将管芯，电线和电绝缘材料封装在一个 导热材料。 公开和要求保护其他实施例。

公开(公告)号：US20040266066A1

公开(公告)日：2004-12-30

申请号：US10874239

申请日：2004-06-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tong Hong Wang

IPC: H01L021/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: A bump structure is applicable for disposing above a semiconductor wafer, which has a plurality of bonding pads and a passivation exposing the bonding pads on which a plurality of patterned under bump metallurgy layers are formed. It is characterized that the bump structure is made of a first bump and a second bump, and the bump structure is disposed on one of the patterned under bump metallurgy layer wherein the second bump covers the first bump and the melting point of the second bump is below the melting point of the first bump. In addition, a manufacturing method of the bump structure is provided.

Abstract translation: 凸块结构适用于设置在具有多个接合焊盘的半导体晶片上方，以及露出其上形成有多个图案化的凸块下金属层的接合焊盘的钝化。 其特征在于，所述凸块结构由第一凸块和第二凸块构成，并且所述凸块结构设置在所述图案化凸块冶金层中的一个上，其中所述第二凸块覆盖所述第一凸块，并且所述第二凸块的熔点为 低于第一凸点的熔点。 此外，提供了凸块结构的制造方法。

公开(公告)号：US20040266048A1

公开(公告)日：2004-12-30

申请号：US10899474

申请日：2004-07-26

Applicant: Honeywell International Inc.

Inventor： William P. Platt ,  Carol M. Ford

IPC: H01L021/44 ,  H01L029/82

CPC classification number: B81C1/00269 ,  B81C2203/0109 ,  B81C2203/038 ,  H01L2224/48247

Abstract: A method of bonding and packaging components of Micro-Electro-Mechanical Systems (MEMS) and MEMS based devices using a Solid-Liquid InterDiffusion (SLID) process is provided. A micro-machine is bonded to a micro-machine chip using bonding materials. A layer of chromium is first deposited onto surfaces of the micro-machine and the micro-machine chip followed by a layer of gold. Subsequently, a layer of indium is deposited between the layers of gold, and the surface of the micro-machine is pressed against the surface of the micro-machine chip forming a gold-indium alloy to serve as a bond between the micro-machine and the micro-machine chip. In addition, a cover is bonded to the micro-machine chip in the same manner providing a hermetic seal for the MEMS based device.

公开(公告)号：US20040264148A1

公开(公告)日：2004-12-30

申请号：US10609052

申请日：2003-06-27

Inventor： William Edward Burdick JR. ,  Sandeep Shrikant Tonapi ,  Joseph Alfred Iannotti ,  James Enrico Sabatini

IPC: H01L021/44 ,  H05K001/00 ,  H05K007/08

CPC classification number: H05K1/189 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/00014 ,  H05K1/0203 ,  H01L2224/0401

Abstract: An electronic component assembly includes a flexible printed circuit, and further includes two components disposed on the flexible printed circuit, having electrical connections with the flexible printed circuit. The flexible layer is folded so that the components face each other and a thermal management device is disposed between the components. The thermal management device may be glued by a thermally conducting adhesive or otherwise held in a stable arrangement, in order to remove the heat generated from the components.

Abstract translation: 电子部件组件包括柔性印刷电路，并且还包括设置在柔性印刷电路上的两个部件，其具有与柔性印刷电路的电连接。 柔性层被折叠，使得这些部件彼此面对，并且热管理装置设置在部件之间。 热管理装置可以由导热粘合剂胶合或以其它方式保持在稳定的布置中，以便去除由部件产生的热量。

公开(公告)号：US20040262760A1

公开(公告)日：2004-12-30

申请号：US10820856

申请日：2004-04-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Min-Lung Huang

IPC: H01L021/44 ,  H01L023/48 ,  H01L029/40

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the bonding pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes tin-copper alloy.

Abstract translation: 凸起下的冶金结构适用于晶片上方和晶片的焊盘上方。 晶片包括钝化层和凸块下金属结构。 钝化层露出接合焊盘，并且在接合焊盘上顺序地形成包括粘合剂层，第一阻挡层，润湿层和第二阻挡层的凸起下金属结构。 具体地说，第二屏障的材料主要包括锡 - 铜合金。