Invention Application
- Patent Title: Self-synchronizing pseudorandom bit sequence checker
- Patent Title (中): 自同步伪随机比特序列检验器
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Application No.: US10650222Application Date: 2003-08-28
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Publication No.: US20050050419A1Publication Date: 2005-03-03
- Inventor: Mohit Kapur , Seongwon Kim
- Applicant: Mohit Kapur , Seongwon Kim
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H04L1/20 ; H04L1/24

Abstract:
Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
Public/Granted literature
- US07412640B2 Self-synchronizing pseudorandom bit sequence checker Public/Granted day:2008-08-12
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