发明申请
US20050051605A1 Process of manufacturing a solder-fill for applying to semiconductor package
审中-公开
制造用于半导体封装的焊料填充的工艺
- 专利标题： Process of manufacturing a solder-fill for applying to semiconductor package
- 专利标题（中）： 制造用于半导体封装的焊料填充的工艺
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申请号： US10959100申请日： 2004-10-07
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公开(公告)号： US20050051605A1公开(公告)日： 2005-03-10
- 发明人: Ho-Young Lee
- 申请人： Ho-Young Lee
- 优先权： KR2002-0056807 20020918; KR2002-0057331 20020919; KR2002-0068776 20021107
- 主分类号： B23K3/06
- IPC分类号： B23K3/06 ; H01L21/56 ; H01L21/60 ; H01L23/498 ; H05K3/34 ; B23K31/02
摘要：
A process of manufacturing a solder-fill is comprised of: arranging a plurality of wire or rod shaped solder bump material to match with the connection pattern of semiconductor chip and PCB in a container, filling a liquid state of under-fill material into the container, solidifying the under-fill material in the container, and slicing the solidified under-fill material and solder bump material with a uniform thickness.
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