An analogue-to-digital sigma-delta modulator for converting analogue input signals to digital output signals comprises a feedback path (1, 101, 201) for producing analogue feedback signals that are a function of the digital output signals (y, Y), an ‘N’-stage (‘N’≧2) integrator path (9 to 14, 109 to 114) for integrating analogue difference signals that are a difference function of the input signal and the analogue feedback signals, and a quantizer (3, 103) responsive to the signals integrated by the integrator means (9 to 14, 109 to 114) for producing the digital output signals (y, Y) at clock intervals. The feedback path includes ‘N’ feedback stages (15 to 17, 115 to 117) for respective integrator stages (9 to 14, 109 to 114). Each of the ‘N’ feedback stages (15 to 17, 115 to 117) comprises finite impulse response (‘FIR’) filters (15 to 19, 115 to 117), each of the FIR filters being of the same order ‘M’, where ‘M’ is at least two; at least the filter (15, 115) of the feedback stage that feeds back to the first integrator stage is a low pass filter. The integrator stages may be discrete-time integrators; the FIR filters reduce their sensitivity to feedback voltage step changes that would cause non-linearities due to slew-rate limitations. Alternatively, the integrator stages may be continuous-time integrators; the FIR filters reduce their sensitivity to clock pulse jitters. In the embodiment shown in FIG. 11, the first integrator stage (109, 110) is a continuous-time integrator stage, and the remainder of the integrator stages (11 to 14) are discrete-time integrator stages.