发明申请
- 专利标题: Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same
- 专利标题(中): 具有至少三个高k电介质层的模拟电容器及其制造方法
-
申请号: US10874461申请日: 2004-06-23
-
公开(公告)号: US20050063141A1公开(公告)日: 2005-03-24
- 发明人: Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
- 申请人: Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon , Weon-Hong Kim
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 优先权: KR03-65272 20030919
- 主分类号: H01L27/02
- IPC分类号: H01L27/02 ; H01G4/20 ; H01L21/02 ; H01L21/316 ; H01L29/00
摘要:
There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer. Therefore, with use of the at least three high-k dielectric layers, the VCC characteristics and the leakage current characteristics of the analog capacitor can be optimized.
公开/授权文献
信息查询
IPC分类: