A method of forming an interconnect structure (e.g., copper interconnect structure, and the like) on a semiconductor substrate. The interconnect structure is formed by depositing within trenches and openings formed in an inter-metal dielectric (IMD) layer a barrier layer and a conductive material. Thereafter, the interconnect structure is planarized using a two-step process whereby excess conductive material on the IMD material is removed during the first step using a chemical mechanical polishing (CMD) process. In the second step the barrier layer is removed using a plasma etch process. The barrier layer is removed using a gas mixture including a halogen-containing gas.