公开(公告)号：US20120083134A1

公开(公告)日：2012-04-05

申请号：US13234020

申请日：2011-09-15

申请人： Hui-Jung WU ,  Kay SONG ,  Victor LU ,  Kie Jin PARK ,  Wai-Fan YAU

发明人： Hui-Jung WU ,  Kay SONG ,  Victor LU ,  Kie Jin PARK ,  Wai-Fan YAU

IPC分类号： H01L21/30 ,  B05C11/00

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76862 ,  H01L21/76864

摘要： Systems, methods, and apparatus for depositing a protective layer on a wafer substrate are disclosed. In one aspect, a protective layer is deposited over a surface of a wafer substrate using a process configured to produce substantially less damage in the wafer substrate than a first plasma-assisted deposition process. The protective layer is less than about 100 Angstroms thick. A barrier layer is deposited over the protective layer using the first plasma-assisted deposition process.

摘要翻译： 公开了用于在晶片衬底上沉积保护层的系统，方法和装置。 在一个方面，使用被配置为在第一等离子体辅助沉积工艺中产生比晶片衬底显着更少的损伤的工艺，在晶片衬底的表面上沉积保护层。 保护层小于约100埃厚。 使用第一等离子体辅助沉积工艺在保护层上沉积阻挡层。

公开(公告)号：US07658969B2

公开(公告)日：2010-02-09

申请号：US11564354

申请日：2006-11-29

申请人： Ajay Kumar ,  Virinder Grewal ,  Wai-Fan Yau

发明人： Ajay Kumar ,  Virinder Grewal ,  Wai-Fan Yau

IPC分类号： C23C16/00

CPC分类号： C23C16/509 ,  C23C16/56 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32706 ,  H01L21/67069 ,  H01L21/67207

摘要： A method and apparatus for process integration in manufacture of a ask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.

摘要翻译： 公开了一种用于制造光掩模中的工艺集成的方法和装置。 在一个实施例中，适用于制造光掩模中的工艺集成的集群工具，该光掩模包括与至少一个硬掩模沉积室耦合的真空传送室和被配置用于蚀刻铬的至少一个等离子体室。 在另一个实施例中，用于制造光掩模中的工艺集成的方法包括在第一处理室中的基板上沉积硬掩模，在衬底上沉积抗蚀剂层，图案化抗蚀剂层，通过形成在 图案化的抗蚀剂层在第二室中; 以及通过在第三室中形成在硬掩模中的孔蚀刻铬层。

公开(公告)号：US07560377B2

公开(公告)日：2009-07-14

申请号：US11087393

申请日：2005-03-22

申请人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

发明人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

IPC分类号： H01L21/4763 ,  H01L21/461

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2221/1031 ,  Y10T428/24926 ,  Y10T428/31663

摘要： A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

摘要翻译： 一种通过有机硅化合物和包含碳的氧化气体以恒定的RF功率水平的反应沉积低介电常数膜的方法和装置。 在与有机硅化合物混合之前，优选在单独的微波室内可以提高氧化气体的离解，以帮助控制沉积膜的碳含量。 氧化的有机硅烷或有机硅氧烷膜具有良好的屏障性能，用作邻近其它介电层的衬垫层或盖层。 氧化的有机硅烷或有机硅氧烷膜也可以用作蚀刻停止层和用于制造双镶嵌结构的金属间介电层。 氧化的有机硅烷或有机硅氧烷膜也在不同的介电层之间提供优异的粘附性。

公开(公告)号：US20080064225A1

公开(公告)日：2008-03-13

申请号：US11877483

申请日：2007-10-23

申请人： Wai-Fan Yau ,  David Cheung ,  Shin-Puu Jeng ,  Kuowei Liu ,  Yung-Cheng Yu

发明人： Wai-Fan Yau ,  David Cheung ,  Shin-Puu Jeng ,  Kuowei Liu ,  Yung-Cheng Yu

IPC分类号： H01L21/469

CPC分类号： H01L21/76834 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76837

摘要： A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.

公开(公告)号：US20070119373A1

公开(公告)日：2007-05-31

申请号：US11564354

申请日：2006-11-29

申请人： Ajay Kumar ,  Virinder Grewal ,  Wai-Fan Yau

发明人： Ajay Kumar ,  Virinder Grewal ,  Wai-Fan Yau

IPC分类号： C23C16/00

CPC分类号： C23C16/509 ,  C23C16/56 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32706 ,  H01L21/67069 ,  H01L21/67207

摘要： A method and apparatus for process integration in manufacture of a ask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.

摘要翻译： 公开了一种用于制造光掩模中的工艺集成的方法和装置。 在一个实施例中，适用于制造光掩模中的工艺集成的集群工具，该光掩模包括与至少一个硬掩模沉积室耦合的真空传送室和被配置用于蚀刻铬的至少一个等离子体室。 在另一个实施例中，用于制造光掩模中的工艺集成的方法包括在第一处理室中的基板上沉积硬掩模，在衬底上沉积抗蚀剂层，图案化抗蚀剂层，通过形成在 图案化的抗蚀剂层在第二室中; 以及通过在第三室中形成在硬掩模中的孔蚀刻铬层。

公开(公告)号：US20070031609A1

公开(公告)日：2007-02-08

申请号：US11192997

申请日：2005-07-29

申请人： Ajay Kumar ,  Virinder Grewal ,  Wai-Fan Yau

发明人： Ajay Kumar ,  Virinder Grewal ,  Wai-Fan Yau

IPC分类号： C23C16/00 ,  C23C14/00 ,  B05C5/00 ,  B05D3/00

CPC分类号： C23C16/509 ,  C23C16/56 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32706 ,  H01L21/67069 ,  H01L21/67207

摘要： A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.

摘要翻译： 公开了一种用于制造光掩模中的工艺集成的方法和装置。 在一个实施例中，适用于制造光掩模中的工艺集成的集群工具，该光掩模包括与至少一个硬掩模沉积室耦合的真空传送室和被配置用于蚀刻铬的至少一个等离子体室。 在另一个实施例中，用于制造光掩模中的工艺集成的方法包括在第一处理室中的基板上沉积硬掩模，在衬底上沉积抗蚀剂层，图案化抗蚀剂层，通过形成在 图案化的抗蚀剂层在第二室中; 以及通过在第三室中形成在硬掩模中的孔蚀刻铬层。

公开(公告)号：US07070657B1

公开(公告)日：2006-07-04

申请号：US09418818

申请日：1999-10-15

申请人： David Cheung ,  Joe Feng ,  Judy H. Huang ,  Wai-Fan Yau

发明人： David Cheung ,  Joe Feng ,  Judy H. Huang ,  Wai-Fan Yau

IPC分类号： C23C16/52 ,  C23F1/00 ,  H01L21/306

CPC分类号： G03F7/091

摘要： This invention provides a stable process for depositing an antireflective layer. Helium gas is used to lower the deposition rate of plasma-enhanced silane oxide, silane oxynitride, and silane nitride processes. Helium is also used to stabilize the process, so that different films can be deposited. The invention also provides conditions under which process parameters can be controlled to produce antireflective layers with varying optimum refractive index, absorptive index, and thickness for obtaining the desired optical behavior.

摘要翻译： 本发明提供一种用于沉积抗反射层的稳定方法。 氦气用于降低等离子体增强硅烷氧化物，硅氮氧化物和氮化硅工艺的沉积速率。 氦也用于稳定工艺，使得可以沉积不同的膜。 本发明还提供了可以控制工艺参数以产生具有变化的最佳折射率，吸收指数和厚度以获得所需光学行为的抗反射层的条件。

公开(公告)号：US20050079703A1

公开(公告)日：2005-04-14

申请号：US10683143

申请日：2003-10-09

申请人： Hui Chen ,  Chun Yan ,  Wai-Fan Yau

发明人： Hui Chen ,  Chun Yan ,  Wai-Fan Yau

IPC分类号： C23F3/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/02074 ,  C23F3/04 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/7684

摘要： A method of forming an interconnect structure (e.g., copper interconnect structure, and the like) on a semiconductor substrate. The interconnect structure is formed by depositing within trenches and openings formed in an inter-metal dielectric (IMD) layer a barrier layer and a conductive material. Thereafter, the interconnect structure is planarized using a two-step process whereby excess conductive material on the IMD material is removed during the first step using a chemical mechanical polishing (CMD) process. In the second step the barrier layer is removed using a plasma etch process. The barrier layer is removed using a gas mixture including a halogen-containing gas.

摘要翻译： 在半导体衬底上形成互连结构（例如，铜互连结构等）的方法。 互连结构通过在形成于金属间电介质（IMD）层的沟槽和开口内沉积阻挡层和导电材料而形成。 此后，使用两步法将互连结构平坦化，由此在第一步骤期间使用化学机械抛光（CMD）工艺除去IMD材料上的过量导电材料。 在第二步骤中，使用等离子体蚀刻工艺去除阻挡层。 使用包含含卤素气体的气体混合物除去阻挡层。

公开(公告)号：US06858153B2

公开(公告)日：2005-02-22

申请号：US10011368

申请日：2001-11-05

申请人： Claes H. Bjorkman ,  Min Melissa Yu ,  Hongquing Shan ,  David W. Cheung ,  Wai-Fan Yau ,  Kuowei Liu ,  Nasreen Gazala Chapra ,  Gerald Yin ,  Farhad K. Moghadam ,  Judy H. Huang ,  Dennis Yost ,  Betty Tang ,  Yunsang Kim

发明人： Claes H. Bjorkman ,  Min Melissa Yu ,  Hongquing Shan ,  David W. Cheung ,  Wai-Fan Yau ,  Kuowei Liu ,  Nasreen Gazala Chapra ,  Gerald Yin ,  Farhad K. Moghadam ,  Judy H. Huang ,  Dennis Yost ,  Betty Tang ,  Yunsang Kim

IPC分类号： H01L21/302 ,  A01C15/02 ,  A01C17/00 ,  C23C16/40 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  C23F1/00

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/3121 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829

摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

摘要翻译： 沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。 电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。 具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。 用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

公开(公告)号：US06743737B2

公开(公告)日：2004-06-01

申请号：US10226717

申请日：2002-08-22

申请人： Wai-Fan Yau ,  David Cheung ,  Nasreen Gazala Chopra ,  Yung-Cheng Lu ,  Robert Mandal ,  Farhad Moghadam

发明人： Wai-Fan Yau ,  David Cheung ,  Nasreen Gazala Chopra ,  Yung-Cheng Lu ,  Robert Mandal ,  Farhad Moghadam

IPC分类号： H01L2131

CPC分类号： H01L21/02211 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/3125 ,  H01L21/31633 ,  H01L21/76807

摘要： A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10 W to about 500 W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.

摘要翻译： 用于沉积低介电常数膜的方法和装置包括沉积氧化硅基膜，优选通过有机硅化合物和氧化气体以约10W至约500W的低RF功率水平反应，暴露基于氧化硅的 膜与水或疏水赋予性表面活性剂如六甲基二硅氮烷，并在升高的温度下固化氧化硅基膜。 可以在单独的微波室中增加氧化气体的离解，以有助于控制沉积膜的碳含量。 氧化硅系膜的耐湿性提高。