A plasma display panel can reduce a discharge delay in address discharge, thereby performing high-speed addressing in a stable manner. A front substrate (1) and a back substrate (2) are disposed to face each other, and a discharge space (3) is formed and partitioned by barrier ribs (10) so as to form priming discharge cells (17) and main discharge cells (11). A clearance (19) is provided between the barrier ribs (10) of the priming discharge cells (17) and the front substrate (1), and priming particles generated in the priming discharge cells (17) are supplied to the main discharge cells (11) through the clearance (19), whereby a PDP performing high-speed addressing is obtained.