发明申请
- 专利标题: Method of manufacturing a semiconductor device
- 专利标题(中): 制造半导体器件的方法
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申请号: US10986896申请日: 2004-11-15
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公开(公告)号: US20050104098A1公开(公告)日: 2005-05-19
- 发明人: Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
- 申请人: Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
- 优先权: JP2003-384654 20031114
- 主分类号: H01L21/76
- IPC分类号: H01L21/76 ; H01L21/336 ; H01L21/762 ; H01L21/8234 ; H01L21/8238 ; H01L27/04 ; H01L27/08 ; H01L27/092 ; H01L29/45 ; H01L29/78 ; H01L27/01 ; H01L29/94 ; H01L31/0392
摘要:
With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions aced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain sides in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
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