公开(公告)号：US08169047B2

公开(公告)日：2012-05-01

申请号：US12205622

申请日：2008-09-05

申请人： Kunihiko Kato ,  Hideki Yasuoka ,  Masatoshi Taya ,  Masami Koketsu

发明人： Kunihiko Kato ,  Hideki Yasuoka ,  Masatoshi Taya ,  Masami Koketsu

IPC分类号： H01L29/66

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/417

摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

摘要翻译： 本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。 半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区 形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域 在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。 阳极导体膜和n型阴极区彼此肖特基耦合。

公开(公告)号：US20100244137A1

公开(公告)日：2010-09-30

申请号：US12813144

申请日：2010-06-10

申请人： Keiichi YOSHIZUMI ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

发明人： Keiichi YOSHIZUMI ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

IPC分类号： H01L27/06 ,  H01L23/60

CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L21/823857 ,  H01L28/20 ,  H01L28/40

摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

摘要翻译： 尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。 在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。 由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

公开(公告)号：US07393737B2

公开(公告)日：2008-07-01

申请号：US11500381

申请日：2006-08-08

申请人： Keiichi Yoshizumi ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

发明人： Keiichi Yoshizumi ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/82

CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L21/823857 ,  H01L28/20 ,  H01L28/40

摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

摘要翻译： 尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。 在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。 由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

公开(公告)号：US20050104098A1

公开(公告)日：2005-05-19

申请号：US10986896

申请日：2004-11-15

申请人： Hideki Yasuoka ,  Keiichi Yoshizumi ,  Masami Koketsu

发明人： Hideki Yasuoka ,  Keiichi Yoshizumi ,  Masami Koketsu

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L27/01 ,  H01L29/94 ,  H01L31/0392

CPC分类号： H01L29/66659 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/456 ,  H01L29/7835

摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions aced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain sides in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.

摘要翻译： 为了抑制或防止具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应，n + +型半导体区域具有与p < 用于高击穿电压pMIS的源极和漏极的+ 型半导体区域设置在高频沟道区域的栅极宽度方向的两端的沟槽型隔离部分之间的边界区域中 击穿电压pMIS和半导体衬底在远离p型 - 半导体区域的位置处，每个具有高的击穿电压pMIS的场弛豫功能，以便不接触p型 - 型半导体区域（特别是在漏极侧）。 n + +型半导体区域延伸到比沟槽型隔离部分更深的位置。

公开(公告)号：US08604583B2

公开(公告)日：2013-12-10

申请号：US13438190

申请日：2012-04-03

申请人： Kunihiko Kato ,  Hideki Yasuoka ,  Masatoshi Taya ,  Masami Koketsu

发明人： Kunihiko Kato ,  Hideki Yasuoka ,  Masatoshi Taya ,  Masami Koketsu

IPC分类号： H01L29/66

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/417

摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

摘要翻译： 本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。 半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区 形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域 在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。 阳极导体膜和n型阴极区彼此肖特基耦合。

公开(公告)号：US08324706B2

公开(公告)日：2012-12-04

申请号：US12813144

申请日：2010-06-10

申请人： Keiichi Yoshizumi ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

发明人： Keiichi Yoshizumi ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

IPC分类号： H01L21/70

CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L21/823857 ,  H01L28/20 ,  H01L28/40

摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

摘要翻译： 尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。 在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。 由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

公开(公告)号：US08314502B2

公开(公告)日：2012-11-20

申请号：US13081208

申请日：2011-04-06

申请人： Masami Koketsu ,  Toshiaki Sawada

发明人： Masami Koketsu ,  Toshiaki Sawada

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

摘要翻译： 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。

公开(公告)号：US20120187520A1

公开(公告)日：2012-07-26

申请号：US13438190

申请日：2012-04-03

申请人： Kunihiko KATO ,  Hideki YASUOKA ,  Masatoshi TAYA ,  Masami KOKETSU

发明人： Kunihiko KATO ,  Hideki YASUOKA ,  Masatoshi TAYA ,  Masami KOKETSU

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/417

摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

摘要翻译： 本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。 半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区 形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域 在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。 阳极导体膜和n型阴极区彼此肖特基耦合。

公开(公告)号：US20110180877A1

公开(公告)日：2011-07-28

申请号：US13081208

申请日：2011-04-06

申请人： Masami KOKETSU ,  Toshiaki Sawada

发明人： Masami KOKETSU ,  Toshiaki Sawada

IPC分类号： H01L23/544 ,  H01L23/48 ,  H01L23/498

CPC分类号： H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

摘要翻译： 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。

公开(公告)号：US20080220580A1

公开(公告)日：2008-09-11

申请号：US12122717

申请日：2008-05-18

申请人： Kunihiko KATO ,  Masami KOKETSU ,  Shigeya TOYOKAWA ,  Keiichi YOSHIZUMI ,  Hideki YASUOKA ,  Yasuhiro TAKEDA

发明人： Kunihiko KATO ,  Masami KOKETSU ,  Shigeya TOYOKAWA ,  Keiichi YOSHIZUMI ,  Hideki YASUOKA ,  Yasuhiro TAKEDA

IPC分类号： H01L21/8236

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0629 ,  H01L28/40

摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

摘要翻译： 提供一种制造半导体集成电路器件的方法，该半导体集成电路器件在相同的衬底上具有高击穿电压MISFET和低击穿电压MISFET。 预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和 在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。 可以减少半导体集成电路器件的制造步骤的数量。