发明申请
US20050104644A1 Digital delay device, digital oscillator clock signal generator and memory interface
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数字延时器，数字振荡器时钟信号发生器和存储器接口
- 专利标题： Digital delay device, digital oscillator clock signal generator and memory interface
- 专利标题（中）： 数字延时器，数字振荡器时钟信号发生器和存储器接口
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申请号： US10957211申请日： 2004-10-01
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公开(公告)号： US20050104644A1公开(公告)日： 2005-05-19
- 发明人: Luc Montperrus , Philippe Boucard , Jean-Jacques Lecler
- 申请人： Luc Montperrus , Philippe Boucard , Jean-Jacques Lecler
- 优先权： FRFR0311517 20031001
- 主分类号： H03K3/03
- IPC分类号： H03K3/03 ; H03K5/13 ; H03L7/081 ; H03L7/099 ; H03H11/26
摘要：
Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.
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