发明申请
US20050176214A1 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
失效
为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法
- 专利标题： Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
- 专利标题（中）： 为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法
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申请号： US10772940申请日： 2004-02-05
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公开(公告)号： US20050176214A1公开(公告)日： 2005-08-11
- 发明人: Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
- 申请人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
- 主分类号： H01L21/76
- IPC分类号： H01L21/76 ; H01L21/762 ; H01L21/763
摘要：
A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.
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