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    High density MIM capacitor structure and fabrication process
    2.
    发明授权
    High density MIM capacitor structure and fabrication process 有权
    高密度MIM电容器结构及制造工艺

    公开(公告)号：US07317221B2

    公开(公告)日：2008-01-08

    申请号：US10729034

    申请日：2003-12-04

    申请人： Kuan-Lun Chang ,  Chuan-Ying Lee ,  Chun-Hon Chen

    发明人： Kuan-Lun Chang ,  Chuan-Ying Lee ,  Chun-Hon Chen

    IPC分类号： H01L29/72

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

    摘要： A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.

    摘要翻译： 一种用于形成MIM电容器结构的叠层集成电路（IC）MIM电容器结构及方法，包括形成在包括第一上电极部分和第一下电极部分的第一IMD层中的第一MIM电容器结构; 至少第二MIM电容器结构，以层叠的关系布置在包括第二上电极和第二下电极的上覆IMD层中，以形成MIM电容器堆叠; 其中，所述第一下部电极布置成共同的电信号通信，包括金属填充的通孔与所述第二上部电极和所述第一上部电极被布置成与所述第二下部电极共同的电信号通信。

    Semiconductor layout structure for ESD protection circuits
    3.
    发明授权
    Semiconductor layout structure for ESD protection circuits 有权
    ESD保护电路的半导体布局结构

    公开(公告)号：US07238969B2

    公开(公告)日：2007-07-03

    申请号：US11152440

    申请日：2005-06-14

    申请人： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

    发明人： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

    IPC分类号： H01L29/72 ,  H01L29/74 ,  H01L31/111 ,  H01L23/62

    CPC分类号： H01L27/0262

    摘要： A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

    摘要翻译： 公开了一种用于静电放电（ESD）保护电路的半导体布局结构。 半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流 触发可控硅整流器，以在ESD事件期间耗散ESD电荷。 第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。

    Method for forming a bipolar junction transistor
    4.
    发明授权
    Method for forming a bipolar junction transistor 失效
    用于形成双极结型晶体管的方法

    公开(公告)号：US5869380A

    公开(公告)日：1999-02-09

    申请号：US110424

    申请日：1998-07-06

    申请人： Kuan-Lun Chang

    发明人： Kuan-Lun Chang

    IPC分类号： H01L21/331 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L29/7322

    摘要： A bipolar junction transistor structure and method of forming the bipolar junction transistor structure comprising an intrinsic base surrounded by a base link and an extrinsic base surrounding the base link. An emitter is formed above the base. The extrinsic base, base link, and intrinsic base are formed using ion implantation. A single layer of doped polysilicon is used to provide the doping source for the emitter and a collector contact. Silicide contacts to the emitter, collector, or base are not required or used.

    摘要翻译： 一种双极结型晶体管结构以及形成双极结型晶体管结构的方法，该结双极结型晶体管结构包括由基极连接包围的本征基极和围绕基极线的外部基极。 在基底上方形成发射体。 使用离子注入形成外在碱基，碱基连接和固有碱基。 使用单层掺杂多晶硅来为发射极和集电极触点提供掺杂源。 不需要或使用与发射极，集电极或基极的硅化物接触。

    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
    6.
    发明授权
    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 失效
    为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法

    公开(公告)号：US07015086B2

    公开(公告)日：2006-03-21

    申请号：US10772940

    申请日：2004-02-05

    申请人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    发明人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76232 ,  H01L21/763

    摘要： A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

    摘要翻译： 已经开发了用于形成由浅沟槽 - 深沟槽构造构成的隔离区域的工艺，其中获得用于隔离区域和半导体衬底中的相邻有源器件区域的平滑顶表面形貌。 该工艺特征最初形成通过第一化学机械抛光工艺平坦化的绝缘体填充的浅沟槽形状，允许在随后形成在绝缘体填充的浅沟槽形状中的窄直径，深沟槽开口期间实现降低的复杂性 半导体衬底的下面部分。 位于深沟槽开口底部的凹陷多晶硅插塞的形成之后，形成位于深沟槽开口的顶部的绝缘体塞，覆盖凹入的多晶硅插塞。 这通过光刻和选择性干法定义程序和第二化学机械抛光程序来实现，从而产生填充的深沟槽开口，表现出光滑的顶表面形貌。

    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
    7.
    发明申请
    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 失效
    为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法

    公开(公告)号：US20050176214A1

    公开(公告)日：2005-08-11

    申请号：US10772940

    申请日：2004-02-05

    申请人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    发明人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

    CPC分类号： H01L21/76232 ,  H01L21/763

    摘要： A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

    摘要翻译： 已经开发了用于形成由浅沟槽 - 深沟槽构造构成的隔离区域的工艺，其中获得用于隔离区域和半导体衬底中的相邻有源器件区域的平滑顶表面形貌。 该工艺特征最初形成通过第一化学机械抛光工艺平坦化的绝缘体填充的浅沟槽形状，允许在随后形成在绝缘体填充的浅沟槽形状中的窄直径，深沟槽开口期间实现降低的复杂性 半导体衬底的下面部分。 位于深沟槽开口底部的凹陷多晶硅插塞的形成之后，形成位于深沟槽开口的顶部的绝缘体塞，覆盖凹入的多晶硅插塞。 这通过光刻和选择性干法定义程序和第二化学机械抛光程序来实现，从而产生填充的深沟槽开口，表现出光滑的顶表面形貌。

    Elimination of implant damage during manufacture of HBT
    8.
    发明授权
    Elimination of implant damage during manufacture of HBT 有权
    在制造HBT期间消除植入物损伤

    公开(公告)号：US06847061B2

    公开(公告)日：2005-01-25

    申请号：US10406120

    申请日：2003-04-03

    申请人： Chun-Lin Tsai ,  Denny D. Tang ,  Chih-Min Chiang ,  Kuan-Lun Chang ,  Tsyr Shyang ,  Ruey-Hsin Liu

    发明人： Chun-Lin Tsai ,  Denny D. Tang ,  Chih-Min Chiang ,  Kuan-Lun Chang ,  Tsyr Shyang ,  Ruey-Hsin Liu

    IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L31/0328 ,  H01L31/072

    CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

    摘要： During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

    摘要翻译： 在常规制造HBT期间，会发生植入物损伤，导致内部基极扩散增强。 通过从单个均匀掺杂的硅 - 锗层制造基极和基极接触面积已经克服了该问题。 代替离子注入步骤来选择性地降低该层离开基极的电阻，选择性地沉积多晶硅层（使用选择性epi沉积）到该部分上。 此外，多晶硅发射极的性能通过将少量相反掺杂型硅驱动到SiGe基极层中的短暂的热退火来增强。

    Forming different depth trenches simultaneously by microloading effect
    9.
    发明授权
    Forming different depth trenches simultaneously by microloading effect 失效
    通过微加载效应同时形成不同深度的沟槽

    公开(公告)号：US5814547A

    公开(公告)日：1998-09-29

    申请号：US944573

    申请日：1997-10-06

    申请人： Kuan-Lun Chang

    发明人： Kuan-Lun Chang

    IPC分类号： H01L21/763 ,  H01L21/8222

    CPC分类号： H01L21/763

    摘要： A new method of forming simultaneously both shallow and deep trenches is described. A pad oxide layer is provided over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A silicon dioxide layer is deposited overlying the silicon nitride layer. A photoresist mask is formed over the silicon dioxide layer wherein the photoresist mask has a first opening having a first width and a second opening having a second width and wherein the second width is larger than the first width. Trench openings are etched through the silicon dioxide, silicon nitride, and pad oxide layers to the underlying semiconductor substrate within the first and second openings. The photoresist mask is removed. The substrate is etched into through the trench openings to form first and second trenches wherein the first trench within the first opening having the first width is a shallow trench having a first depth and wherein the second trench within the second opening having the second width is a deep trench having a second depth greater than the first depth completing the formation of shallow and deep trenches simultaneously in the fabrication of an integrated circuit.

    摘要翻译： 描述了同时形成浅沟槽和深沟槽的新方法。 衬垫氧化物层设置在半导体衬底上。 在衬垫氧化物层上沉积氮化硅层。 沉积氮化硅层上的二氧化硅层。 在二氧化硅层之上形成光致抗蚀剂掩模，其中光致抗蚀剂掩模具有第一宽度的第一开口和具有第二宽度的第二开口，并且其中第二宽度大于第一宽度。 沟槽开口通过二氧化硅，氮化硅和衬垫氧化物层蚀刻到第一和第二开口内的下面的半导体衬底。 去除光致抗蚀剂掩模。 衬底被蚀刻穿过沟槽开口形成第一和第二沟槽，其中具有第一宽度的第一开口内的第一沟槽是具有第一深度的浅沟槽，并且其中具有第二宽度的第二开口内的第二沟槽是 深沟槽具有大于第一深度的第二深度，在制造集成电路的同时完成浅沟槽和深沟槽的形成。