发明申请
US20050190193A1 Apparatus and a method to adjust signal timing on a memory interface
审中-公开
用于调整存储器接口上的信号定时的装置和方法
- 专利标题： Apparatus and a method to adjust signal timing on a memory interface
- 专利标题（中）： 用于调整存储器接口上的信号定时的装置和方法
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申请号： US10791180申请日： 2004-03-01
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公开(公告)号： US20050190193A1公开(公告)日： 2005-09-01
- 发明人: David Freker , Zohar Bogin , Dour Navneet , Anoop Mukker , Tuong Trieu
- 申请人： David Freker , Zohar Bogin , Dour Navneet , Anoop Mukker , Tuong Trieu
- 主分类号： G06F13/00
- IPC分类号： G06F13/00 ; G06F13/16 ; G06F13/372
摘要：
An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.
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