发明申请
US20050199964A1 CMOS circuit including double-insulated-gate field-effect transistors
失效
CMOS电路包括双绝缘栅场效应晶体管
- 专利标题: CMOS circuit including double-insulated-gate field-effect transistors
- 专利标题(中): CMOS电路包括双绝缘栅场效应晶体管
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申请号: US11072401申请日: 2005-03-07
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公开(公告)号: US20050199964A1公开(公告)日: 2005-09-15
- 发明人: Toshihiro Sekigawa , Hanpei Koike , Yongxun Liu , Meishoku Masahara
- 申请人: Toshihiro Sekigawa , Hanpei Koike , Yongxun Liu , Meishoku Masahara
- 专利权人: National Institute of Advanced Industrial Science and Technology
- 当前专利权人: National Institute of Advanced Industrial Science and Technology
- 优先权: JP2004-069789 20040311
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C11/412 ; H01L21/8238 ; H01L21/8244 ; H01L27/092 ; H01L27/11 ; H01L29/76 ; H03K19/0948
摘要:
It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.