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12 条记录 (耗时 0.011 秒)

    SRAM cell
    2.
    发明授权
    SRAM cell 有权
    SRAM单元

    公开(公告)号：US08537603B2

    公开(公告)日：2013-09-17

    申请号：US13384648

    申请日：2010-07-02

    申请人： Toshihiro Sekigawa ,  Yohei Matsumoto ,  Hanpei Koike

    发明人： Toshihiro Sekigawa ,  Yohei Matsumoto ,  Hanpei Koike

    IPC分类号： G11C11/41 ,  G11C11/412

    CPC分类号： H01L27/1104 ,  G11C11/4125

    摘要： The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

    摘要翻译： 本发明提供一种SRAM单元，其不具有对晶体管尺寸的限制，以实现稳定的写入和读取操作，每个端口具有较少数量的控制信号线，并且其可以容易地多端口 读取操作以及写入操作，使得可以通过单个位线执行写入和读取操作。 SRAM单元包括反馈控制晶体管，用于控制特定的两个反相器之间的正反馈电路的连接或断开，连接到单个位线的写入控制晶体管和读取控制晶体管以及连接到读取控制晶体管的读取缓冲晶体管 。

    RECONFIGURABLE INTEGRATED CIRCUIT
    3.
    发明申请
    RECONFIGURABLE INTEGRATED CIRCUIT 有权
    可重构集成电路

    公开(公告)号：US20080282214A1

    公开(公告)日：2008-11-13

    申请号：US12103229

    申请日：2008-04-15

    申请人： Yohei Matsumoto ,  Hanpei Koike

    发明人： Yohei Matsumoto ,  Hanpei Koike

    IPC分类号： G06F17/50 ,  H01L25/00

    CPC分类号： G06F17/5054 ,  G06F2217/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs.A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.

    摘要翻译： 本发明的目的是通过减少SRAM中的漏电流来实现FPGA等可重构集成电路的功耗降低。 提供了一种可重构集成电路，其包括晶体管并且包括具有输入端的第一开关，输出端和控制端，具有连接到第一开关的控制端的存储单元的第一存储器， 关闭第一存储器的电源线或地线，以及第二存储器来控制第二开关，其中当第一开关不被操作时，打开第二开关的值被写入第二存储器，从而关闭 电源线或第一存储器的接地线。

    SRAM CELL
    4.
    发明申请
    SRAM CELL 有权

    公开(公告)号：US20120120717A1

    公开(公告)日：2012-05-17

    申请号：US13384648

    申请日：2010-07-02

    申请人： Toshihiro Sekigawa ,  Yohei Matsumoto ,  Hanpei Koike

    发明人： Toshihiro Sekigawa ,  Yohei Matsumoto ,  Hanpei Koike

    IPC分类号： G11C11/412 ,  G11C11/419

    CPC分类号： H01L27/1104 ,  G11C11/4125

    摘要： The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

    摘要翻译： 本发明提供一种SRAM单元，其不具有对晶体管尺寸的限制，以实现稳定的写入和读取操作，每个端口具有较少数量的控制信号线，并且其可以容易地多端口 读取操作以及写入操作，使得可以通过单个位线执行写入和读取操作。 SRAM单元包括反馈控制晶体管，用于控制特定的两个反相器之间的正反馈电路的连接或断开，连接到单个位线的写入控制晶体管和读取控制晶体管以及连接到读取控制晶体管的读取缓冲晶体管 。

    High-speed and low-power logical unit
    5.
    发明申请
    High-speed and low-power logical unit 审中-公开
    高速和低功率逻辑单元

    公开(公告)号：US20050097496A1

    公开(公告)日：2005-05-05

    申请号：US10951759

    申请日：2004-09-29

    申请人： Hanpei Koike ,  Tadashi Nakagawa ,  Toshihiro Sekigawa

    发明人： Hanpei Koike ,  Tadashi Nakagawa ,  Toshihiro Sekigawa

    IPC分类号： H01L27/04 ,  G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H03K19/094 ,  H03K19/177 ,  G06F9/45

    CPC分类号： G06F17/505 ,  G06F17/5068 ,  H01L27/0207

    摘要： It is an object of the present invention to provide a high-speed and low-power logical unit formed of a master slice integrated circuit, which offers advantages of reducing the cost and time required for designing masks, and in which a faster operation can be achieved while consuming low power by controlling the operation mode of each logical device forming the logical unit according to the operating state of the corresponding logical device. The high-speed and low-power logical unit comprises a plurality of logical devices including control-voltage input terminals for controlling operation modes, a voltage supply circuit for generating a plurality of different control voltages; and a wiring pattern for supplying a control voltage from the voltage supply circuit for controlling each of the logical devices to operate in an operation mode determined according to an operation of the corresponding transistor to the control-voltage input terminal of the corresponding logical device.

    摘要翻译： 本发明的目的是提供一种由主片集成电路形成的高速和低功率逻辑单元，其提供了降低设计掩模所需的成本和时间的优点，并且其中较快的操作可以是 通过根据对应的逻辑设备的操作状态控制形成逻辑单元的每个逻辑设备的操作模式，同时消耗低功率。 高速和低功率逻辑单元包括多个逻辑设备，包括用于控制操作模式的控制电压输入端子，用于产生多个不同控制电压的电压供应电路; 以及用于从电压供给电路提供控制电压的布线图案，用于控制每个逻辑装置以根据相应晶体管的操作确定的操作模式操作到相应的逻辑装置的控制电压输入端。

    SYSTEM FOR CONFIGURING AN INTEGRATED CIRCUIT AND METHOD THEREOF
    7.
    发明申请
    SYSTEM FOR CONFIGURING AN INTEGRATED CIRCUIT AND METHOD THEREOF 有权
    用于配置集成电路的系统及其方法

    公开(公告)号：US20070300201A1

    公开(公告)日：2007-12-27

    申请号：US11759706

    申请日：2007-06-07

    申请人： Yohei MATSUMOTO ,  Hanpei Koike

    发明人： Yohei MATSUMOTO ,  Hanpei Koike

    IPC分类号： G06F17/50 ,  G06F1/24 ,  G06F15/177 ,  H03K17/693 ,  G06F9/00

    CPC分类号： H03K19/17748 ,  G06F17/5054 ,  H03K19/1778

    摘要： With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory device for configuring 102 which holds a plurality of different circuit configurations to be realized on the reconfigurable integrated circuit, the circuit configurations having identical functions but having different performance depending on different probability variables, memory device for testing 103 which holds test data to be achieved by the circuit configuration for the respective function, and a test device 104 for performing a test based on the test data.

    摘要翻译： 关于可重构集成电路，提供了一种用于配置集成电路的系统及其配置方法，其不需要用于变化校正和变化诊断的电路开销。 用于配置集成电路的系统包括可重构集成电路101，用于配置102的存储器件，其保存要在可重构集成电路上实现的多个不同电路配置，该电路配置具有相同的功能，但具有不同的性能，具体取决于不同的 概率变量，用于测试103的存储器件，其存储要通过相应功能的电路配置实现的测试数据;以及测试设备104，用于基于测试数据执行测试。

    CMOS circuit including double-insulated-gate field-effect transistors
    8.
    发明授权
    CMOS circuit including double-insulated-gate field-effect transistors 失效
    CMOS电路包括双绝缘栅场效应晶体管

    公开(公告)号：US07282959B2

    公开(公告)日：2007-10-16

    申请号：US11072401

    申请日：2005-03-07

    申请人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    发明人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    IPC分类号： H03K19/094

    CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L27/1108

    摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

    摘要翻译： 本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。 本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极 场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压 型四端双绝缘栅场效应晶体管。

    CMOS circuit including double-insulated-gate field-effect transistors
    9.
    发明申请
    CMOS circuit including double-insulated-gate field-effect transistors 失效
    CMOS电路包括双绝缘栅场效应晶体管

    公开(公告)号：US20050199964A1

    公开(公告)日：2005-09-15

    申请号：US11072401

    申请日：2005-03-07

    申请人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    发明人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/76 ,  H03K19/0948

    CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L27/1108

    摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

    摘要翻译： 本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。 本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极 场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压 型四端双绝缘栅场效应晶体管。

    Reconfigurable integrated circuit
    10.
    发明授权
    Reconfigurable integrated circuit 有权
    可重构集成电路

    公开(公告)号：US07886250B2

    公开(公告)日：2011-02-08

    申请号：US12103229

    申请日：2008-04-15

    申请人： Yohei Matsumoto ,  Hanpei Koike

    发明人： Yohei Matsumoto ,  Hanpei Koike

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F2217/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs.A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power supply line or a ground line of the first memory, and a second memory to control the second switch, wherein a value to open the second switch is written into the second memory when the first switch is not operated, thereby shutting down the power supply line or the ground line of the first memory.

    摘要翻译： 本发明的目的是通过减少SRAM中的漏电流来实现FPGA等可重构集成电路的功耗降低。 提供了一种可重构集成电路，其包括晶体管并且包括具有输入端的第一开关，输出端和控制端，具有连接到第一开关的控制端的存储单元的第一存储器， 关闭第一存储器的电源线或地线，以及第二存储器来控制第二开关，其中当第一开关不被操作时，打开第二开关的值被写入第二存储器，从而关闭 电源线或第一存储器的接地线。